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PIC16F72 Data Sheet
28-Pin, 8-Bit CMOS FLASH Microcontroller with A/D Converter
2002 Microchip Technology Inc.
DS39597B
Note the following details of the code protection feature on PICmicro(R) MCUs. The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". www..com * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
* *
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS39597B - page ii
2002 Microchip Technology Inc.
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Device Included:
* PIC16F72
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PIC16F72
Pin Diagrams
PDIP, SOIC, SSOP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL *1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA
28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter
High Performance RISC CPU:
* Only 35 single word instructions to learn * All single cycle instructions except for program branches, which are two-cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM) * Pinout compatible to PIC16C72/72A and PIC16F872 * Interrupt capability * Eight-level deep hardware stack * Direct, Indirect and Relative Addressing modes
PIC16F72
Peripheral Features:
* High Sink/Source Current: 25 mA * Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Capture, Compare, PWM (CCP) module - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit * 8-bit, 5-channel analog-to-digital converter * Synchronous Serial Port (SSP) with SPITM (Master/Slave) and I2CTM (Slave) * Brown-out detection circuitry for Brown-out Reset (BOR)
RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKI OSC2/CLKO
1 2 3 4 5 6 7
28 27 26 25 24 23 22 21 20 19 18 PIC16F72 17 16 15 8 9 10 11 12 13 14
RA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5 RB4
QFN
RB3 RB2 RB1 RB0/INT VDD VSS RC7
Special Microcontroller Features:
* 1,000 erase/write cycle FLASH program memory typical * Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options * In-Circuit Serial ProgrammingTM (ICSPTM) via 2 pins * Processor read access to program memory
CMOS Technology:
* * * * * Low power, high speed CMOS FLASH technology Fully static design Wide operating voltage range: 2.0V to 5.5V Industrial temperature range Low power consumption: - < 0.6 mA typical @ 3V, 4 MHz - 20 A typical @ 3V, 32 kHz - < 1 A typical standby current
2002 Microchip Technology Inc.
RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6
DS39597B-page 1
PIC16F72
Key Reference Manual Features Operating Frequency RESETS and (Delays) FLASH Program Memory - (14-bit words, 1000 E/W cycles) Data Memory - RAM (8-bit bytes) Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications 8-bit A/D Converter Instruction Set (No. of Instructions) PIC16F72 DC - 20 MHz POR, BOR, (PWRT, OST) 2K 128 8 PORTA, PORTB, PORTC Timer0, Timer1, Timer2 1 SSP 5 channels 35
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DS39597B-page 2
2002 Microchip Technology Inc.
PIC16F72
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 7 3.0 I/O Ports ..................................................................................................................................................................................... 21 4.0 Reading Program Memory ......................................................................................................................................................... 27 5.0 Timer0 Module ........................................................................................................................................................................... 29 6.0 Timer1 Module ........................................................................................................................................................................... 31 7.0 Timer2 Module ........................................................................................................................................................................... 35 8.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 37 9.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 43 10.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 53 11.0 Special Features of the CPU...................................................................................................................................................... 59 12.0 Instruction Set Summary ............................................................................................................................................................ 73 13.0 Development Support................................................................................................................................................................. 81 14.0 Electrical Characteristics ............................................................................................................................................................ 87 15.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 107 www..com 16.0 Package Marking Information................................................................................................................................................... 117 Appendix A: Revision History ........................................................................................................................................................ 123 Appendix B: Conversion Considerations........................................................................................................................................ 123 Index .................................................................................................................................................................................................. 125 On-Line Support................................................................................................................................................................................. 131 Reader Response .............................................................................................................................................................................. 132 Product Identification System ............................................................................................................................................................ 133
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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2002 Microchip Technology Inc.
DS39597B-page 3
PIC16F72
NOTES:
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DS39597B-page 4
2002 Microchip Technology Inc.
PIC16F72
1.0 DEVICE OVERVIEW
This document contains device specific information for the operation of the PIC16F72 device. Additional information may be found in the PICmicroTM Mid-Range MCU Reference Manual (DS33023), which may be downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F72 belongs to the Mid-Range family of the PICmicro devices. A block diagram of the device is shown in Figure 1-1. The program memory contains 2K words, which translate to 2048 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 128 bytes. There are 22 I/O pins that are user configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: * External interrupt * Change on PORTB interrupt * Timer0 clock input * Timer1 clock/oscillator * Capture/Compare/PWM * A/D converter * SPI/I2C Table 1-1 details the pinout of the device with descriptions and details for each pin.
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FIGURE 1-1:
PIC16F72 BLOCK DIAGRAM
13 Program Counter FLASH Program Memory 2K x 14 Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3 RB4 RB5 RB6/PGC RB7/PGD RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7
8-Level Stack (13-bit)
RAM File Registers 128 x 8 RAM Addr(1) 9
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3 PORTC
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
W reg
MCLR
VDD, VSS
Timer0
Timer1
Timer2
A/D
Synchronous Serial Port
CCP1
Note 1: Higher order bits are from the STATUS register.
2002 Microchip Technology Inc.
DS39597B-page 5
PIC16F72
TABLE 1-1:
Pin Name
PIC16F72 PINOUT DESCRIPTION
PDIP, SOIC, SSOP Pin# 9 10 MLF Pin# I/O/P Type Buffer Type Description
OSC1/CLKI OSC2/CLKO
6 7
I O
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, the OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0. RA1 can also be analog input1. RA2 can also be analog input2. RA3 can also be analog input3 or analog reference voltage. RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
MCLR/VPP
1
26
I/P
ST
RA0/AN0 www..com RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS
2 3 4 5 6 7
27 28 1 2 3 4
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6/PGC RB7/PGD RC0/T1OSO/ T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 VSS VDD
21 22 23 24 25 26 27 28 11 12 13 14 15 16 17 18 8, 19 20
18 19 20 21 22 23 24 25 8 9 10 11 12 13 14 15 5, 16 17
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) ST ST ST ST ST ST ST ST -- --
RB0 can also be the external interrupt pin.
Interrupt-on-change pin. Interrupt-on-change pin. Interrupt-on-change pin. Serial programming clock. Interrupt-on-change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input. RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode).
Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS39597B-page 6
2002 Microchip Technology Inc.
PIC16F72
2.0 MEMORY ORGANIZATION
2.2 Data Memory Organization
There are two memory blocks in the PIC16F72 device. These are the program memory and the data memory. Each block has separate buses so that concurrent access can occur. Program memory and data memory are explained in this section. Program memory can be read internally by the user code (see Section 4.0). The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the "core" are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module.
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The Data Memory is partitioned into multiple banks that contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. RP1:RP0 00 01 10 11 Bank 0 1 2 3
Additional information on device memory may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain SFRs. Some "high use" SFRs from one bank may be mirrored in another bank, for code reduction and quicker access (e.g., the STATUS register is in Banks 0 - 3).
2.1
Program Memory Organization
PIC16F72 devices have a 13-bit program counter capable of addressing a 8K x 14 program memory space. The address range for this program memory is 0000h 07FFh. Accessing a location above the physically implemented address will cause a wraparound. The RESET Vector is at 0000h and the Interrupt Vector is at 0004h.
2.2.1
GENERAL PURPOSE REGISTER FILE
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK
PC<12:0>
The register file can be accessed either directly, or indirectly, through the File Select Register FSR (see Section 2.5).
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
Stack Level 8 RESET Vector
0000h
User Memory Space
Interrupt Vector
0004h 0005h
On-chip Program Memory 07FFh 0800h
1FFFh
2002 Microchip Technology Inc.
DS39597B-page 7
PIC16F72
FIGURE 2-2: PIC16F72 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC
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File Address Indirect addr.(*) 80h OPTION 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h 88h 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch 8Dh PCON 8Eh 8Fh 90h 91h PR2 92h SSPADD 93h SSPSTAT 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh ADCON1 General A0h Purpose Register BFh 32 Bytes C0h accesses 40h-7Fh
File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch PMDATL PMADRL 10Dh 10Eh PMDATH 10Fh PMADRH 110h
File Address Indirect addr.(*) OPTION PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON
ADRES ADCON0
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
PCLATH INTCON PMCON1
11Fh 120h accesses A0h -BFh
19Fh 1A0h 1BFh
General Purpose Register 96 Bytes
accesses 20h-7Fh
1C0h accesses 40h -7Fh
7Fh Bank 0 Bank 1
FFh Bank 2
17Fh Bank 3
1FFh
Unimplemented data memory locations, read as `0'. * Not a physical register.
DS39597B-page 8
2002 Microchip Technology Inc.
PIC16F72
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section.
TABLE 2-1:
Address Bank 0 00h(1) 01h INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC -- -- INTCON PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON -- ADRES ADCON0 Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details on POR, BOR page:
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP -- RP1 -- RP0 TO PD Z DC C Indirect Data Memory Address Pointer PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read Unimplemented Unimplemented -- GIE -- -- PEIE ADIF -- TMR0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE SSPIF TMR0IF CCP1IF INTF TMR2IF RBIF TMR1IF xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx xxxx xxxx -- -- ---0 0000 0000 000x -0-- 0000 -- xxxx xxxx xxxx xxxx TMR1ON --00 0000 0000 0000 xxxx xxxx SSPM2 SSPM1 SSPM0 0000 0000 xxxx xxxx xxxx xxxx CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 -- xxxx xxxx CHS2 CHS1 CHS0 GO/DONE -- ADON 0000 00-0
19 29,13 18 12 19 21 23 25 -- -- 18 14 16 -- 31 31 31 35 36 43,48 45 38,39,41 38,39,41 37 -- 53 53
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03h(1) 04h(1) 05h 06h 07h 08h 09h 0Bh(1) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h-1Dh 1Eh 1Fh Legend: Note 1: 2: 3:
0Ah(1,2) PCLATH
Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- WCOL -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS Timer2 Module's Register Synchronous Serial Port Receive Buffer/Transmit Register SSPOV SSPEN CKP SSPM3 Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) -- -- CCP1X CCP1Y Unimplemented A/D Result Register ADCS1 ADCS0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. These registers can be addressed from any bank. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. This bit always reads as a `1'.
2002 Microchip Technology Inc.
DS39597B-page 9
PIC16F72
TABLE 2-1:
Address Bank 1 80h(1) 81h 82h(1) 83h(1) 84h(1) 85h 86h INDF OPTION PCL STATUS FSR TRISA TRISB TRISC -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 0000 0000 PD Z DC C 0001 1xxx xxxx xxxx --11 1111 1111 1111 1111 1111 -- -- -- TMR0IE -- Write Buffer for the upper 5 bits of the PC INTE -- RBIE SSPIE TMR0IF CCP1IE INTF TMR2IE RBIF TMR1IE ---0 0000 0000 000x -0-- 0000 -- -- -- -- -- POR BOR ---- --qq -- -- -- 1111 1111 0000 0000 R/W UA BF 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- PCFG2 PCFG1 PCFG0 ---- -000 19 13 18 12 19 21 23 25 -- -- 18 14 15 -- 17 -- -- -- 41 43,48 44 -- -- -- -- -- -- -- -- -- -- 54 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details on POR, BOR page:
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO
Indirect Data Memory Address Pointer -- -- PORTA Data Direction Register
PORTB Data Direction Register PORTC Data Direction Register Unimplemented Unimplemented -- GIE -- -- PEIE ADIE
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88h 89h 8Bh(1) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3:
87h
8Ah(1,2) PCLATH INTCON PIE1 -- PCON -- -- -- PR2 SSPADD SSPSTAT -- -- -- -- -- -- -- -- -- -- ADCON1
Unimplemented -- --
Unimplemented Unimplemented Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. These registers can be addressed from any bank. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. This bit always reads as a `1'.
DS39597B-page 10
2002 Microchip Technology Inc.
PIC16F72
TABLE 2-1:
Address Bank 2 100h(1) 101h 102h(1 103h
(1)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details on POR, BOR page:
Name
INDF TMR0 PCL STATUS FSR -- PORTB -- -- --
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx -- xxxx xxxx -- -- -- -- TMR0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE TMR0IF INTF RBIF ---0 0000 0000 000x xxxx xxxx xxxx xxxx --xx xxxx ---x xxxx Address Register High Byte
19 29 18 12 19 -- 23 -- -- -- 18 14 27 27 27 27
104h(1) 105h 106h 107h 108h 109h
Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- PEIE
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10Ah(1,2) PCLATH 10Bh(1) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(1) 181h 182h(1) 183h(1) 184h(1) 185h 186h 187h 188h 189h 18Bh(1) 18Ch 18Dh 18Eh 18Fh Legend: Note 1: 2: 3: INDF OPTION PCL STATUS FSR -- TRISB -- -- -- INTCON PMDATL PMADRL PMDATH PMADRH
Data Register Low Byte Address Register Low Byte -- -- -- -- Data Register High Byte --
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 0000 0000 PD Z DC C 0001 1xxx xxxx xxxx -- 1111 1111 -- -- -- -- TMR0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- TMR0IF -- INTF -- RBIF RD ---0 0000 0000 000x 1--- ---0 -- 0000 0000 0000 0000 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO
19 13 18 12 19 -- 23 -- -- -- 18 14 27 -- -- --
Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE --
(3)
18Ah(1,2) PCLATH INTCON PMCON1 -- -- --
-- PEIE --
Unimplemented Reserved, maintain clear Reserved, maintain clear
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. These registers can be addressed from any bank. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. This bit always reads as a `1'.
2002 Microchip Technology Inc.
DS39597B-page 11
PIC16F72
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.
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For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see Section 12.0, Instruction Set Summary. Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1,2) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. 2: For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16F72
2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION register is a readable and writable register that contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB.
REGISTER 2-2:
OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
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bit 7
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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2.2.2.3 INTCON Register
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON Register is a readable and writable register that contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
REGISTER 2-3:
INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 TMR0IE R/W-0 INTE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INTF R/W-x RBIF bit 0
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bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16F72
2.2.2.4 PIE1 Register
This register contains the individual enable bits for the peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
U-0
--
R/W-0 ADIE
U-0
--
U-0
--
R/W-0 SSPIE
R/W-0 CCP1IE
R/W-0 TMR2IE
R/W-0 TMR1IE bit 0
bit 7
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bit 7 bit 6
Unimplemented: Read as `0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt Unimplemented: Read as `0' SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5-4 bit 3
bit 2
bit 1
bit 0
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2.2.2.5 PIR1 Register
This register contains the individual flag bits for the Peripheral interrupts.
REGISTER 2-5:
PIR1: PERIPHERAL INTERRUPT FLAG REGISTER 1 (ADDRESS 0Ch)
U-0 -- bit 7 R/W-0 ADIF U-0 -- U-0 -- R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7 bit 6
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Unimplemented: Read as `0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete Unimplemented: Read as `0' SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are a transmission/reception has taken place. 0 = No SSP interrupt condition has occurred CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5-4 bit 3
bit 2
bit 1
bit 0
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2.2.2.6
Note:
PCON Register
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
Note:
BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a `don't care' and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BOREN bit in the Configuration word).
The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR), a Brown-out Reset, an external MCLR Reset and WDT Reset.
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REGISTER 2-6:
PCON: POWER CONTROL REGISTER (ADDRESS 8Eh)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-x BOR bit 0
bit 7-2 bit 1
Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
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PIC16F72
2.3 PCL and PCLATH
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13-bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. Figure 2-3 shows the four situations for the loading of the PC. * Example 1 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). * Example 2 shows how the PC is loaded during a GOTO instruction (PCLATH<4:3> PCH). * Example 3 shows how the PC is loaded during a CALL instruction (PCLATH<4:3> PCH), with the PC loaded (PUSH'd) onto the Top-of-Stack. * Example 4 shows how the PC is loaded during one of the return instructions, where the PC is loaded (POP'd) from the Top-of-Stack.
FIGURE www..com
2-3:
LOADING OF PC IN DIFFERENT SITUATIONS
Example 1 - Instruction with PCL as destination
PCH 12 PC 5 PCLATH<4:0> 8 ALU result PCLATH Stack (13-bits x 8) Top-of-Stack PCL 8 7 0 8 7 PCL 0 Stack (13-bits x 8) Top-of-Stack
Example 2 - GOTO Instruction
PCH 12 PC 2 PCLATH<4:3> 11 11 10
Opcode <10:0>
PCLATH
Example 3 - CALL Instruction
13 PCH 12 PC 2 PCLATH<4:3> 11 11 10 8 7 PCL 0
Stack (13-bits x 8) Top-of-Stack
Opcode <10:0>
PCLATH
Example 4 - RETURN, RETFIE, or RETLW Instruction
13 PCH 12 PC 11 11 10 8 7 PCL 0
Stack (13-bits x 8) Top-of-Stack
Opcode <10:0>
PCLATH
Note: PCLATH is not updated with the contents of PCH.
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PIC16F72
2.3.1 COMPUTED GOTO
2.4
Program Memory Paging
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note, "Implementing a Table Read" (AN556).
2.3.2
STACK
The stack allows a combination of up to eight program calls and interrupts to occur. The stack contains the return address from this branch in program execution.
www..com Mid-range devices have an 8-level deep x 13-bit wide
The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper two bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the return instructions (which POPs the address from the stack). Note: The PIC16F72 device ignores the paging bit PCLATH<4:3>. The use of PCLATH<4:3> as a general purpose read/ write bit is not recommended, since this may affect upward compatibility with future products.
hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSH'd onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POP'd in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSH'd or POP'd. After the stack has been PUSH'd eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). An example of the overwriting of the stack is shown in Figure 2-4.
2.5
Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-1.
FIGURE 2-4:
Stack
STACK MODIFICATION
EXAMPLE 2-1:
Top-of-Stack
movlw movwf clrf incf btfss goto :
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
Push1 Push9 Push2 Push10 Push3 Push4 Push5 Push6 Push7 Push8
NEXT
CONTINUE
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-5. Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
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PIC16F72
FIGURE 2-5: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0 6 From Opcode 0 IRP
Indirect Addressing
7 FSR Register 0
Bank Select Location Select 00 00h 01 80h 10 100h 11 180h
Bank Select
Location Select
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Data Memory(1)
7Fh
FFh
17Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: For register file map detail, see Figure 2-2.
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PIC16F72
3.0 I/O PORTS
FIGURE 3-1:
Data Bus WR Port
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range MCU Reference Manual, (DS33023).
BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
Q VDD VDD
D
CK
Q
P
Data Latch D WR TRIS Q N VSS I/O pin
3.1
PORTA and the TRISA Register
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin www..com an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register, reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as `0'.
CK
Q
VSS Analog Input Mode
TRIS Latch
RD TRIS Q D
TTL Input Buffer
EN RD Port
To A/D Converter
FIGURE 3-2:
Data Bus WR Port
BLOCK DIAGRAM OF RA4/T0CKI PIN
Q Q
D
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
CK
Data Latch
D Q Q
N VSS VSS
I/O pin
EXAMPLE 3-1:
BANKSEL CLRF PORTA PORTA
INITIALIZING PORTA
select bank for PORTA Initialize PORTA by clearing output data latches Select Bank for ADCON1 Configure all pins as digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6> are always read as `0'.
WR TRIS
CK
BANKSEL MOVLW MOVWF MOVLW
MOVWF
; ; ; ; ADCON1 ; 0x06 ; ADCON1 ; 0xCF ; ; ; TRISA ; ; ; ;
TRIS Latch
Schmitt Trigger Input Buffer
RD TRIS
Q D EN EN
RD Port TMR0 Clock Input
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TABLE 3-1:
Name
PORTA FUNCTIONS
Bit# Buffer Function
RA0/AN0 bit 0 TTL Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2 bit 2 TTL Input/output or analog input. RA3/AN3/VREF bit 3 TTL Input/output or analog input or VREF. RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/AN4/SS bit 5 TTL Input/output or analog input or slave select input for synchronous serial port. Legend: TTL = TTL input, ST = Schmitt Trigger input
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TABLE 3-2:
Address 05h 85h 9Fh
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 RA5 -- Bit 4 RA4 -- Bit 3 RA3 -- Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR Value on all other RESETS
Name PORTA TRISA ADCON1
--0x 0000 --0u 0000 --11 1111 --11 1111
PORTA Data Direction Register
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
Note:
When using the SSP module in SPI Slave mode and SS enabled, the A/D Port Configuration Control bits (PCFG2:PCFG0) in the A/D Control Register (ADCON1) must be set to one of the following configurations: 100, 101, 11x.
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PIC16F72
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'd together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
EXAMPLE 3-2:
BANKSEL CLRF PORTB PORTB
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; ; Select bank for PORTB Initialize PORTB by clearing output data latches Select Bank for TRISB Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. This interrupt-on-mismatch feature, together with software configurable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552). RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION<6>).
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BANKSEL MOVLW
TRISB 0xCF
MOVWF
TRISB
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-3:
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD P Weak Pull-up VDD
FIGURE 3-4:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD VDD P Weak Pull-up
RBPU(1) Data Bus WR Port Data Latch D CK TRIS Latch D Q WR TRIS CK Q
RBPU(1) Data Bus I/O pin WR Port Data Latch D CK TRIS Latch D Q WR TRIS CK Q
I/O pin
VSS TTL Input Buffer
VSS TTL Input Buffer
ST Buffer
RD TRIS Q RD Port RB0/INT Schmitt Trigger Buffer RD Port D EN Set RBIF
RD TRIS Q RD Port
Latch D EN Q1
Q From Other RB7:RB4 Pins
D RD Port EN Q3
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>).
RB7:RB6 in Serial Programming Mode
Four of PORTB's pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4)
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>).
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PIC16F72
TABLE 3-3:
Name RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 www..com RB7
PORTB FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 3-4:
Address 06h, 106h 86h, 186h 81h, 181h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 RB7 RBPU Bit 6 RB6 INTEDG Bit 5 RB5 Bit 4 RB4 Bit 3 Bit 2 Bit 1 Bit 0 RB3 PSA RB2 PS2 RB1 PS1 RB0 PS0 Value on POR, BOR xxxx xxxx 1111 1111 1111 1111 Value on all other RESETS uuuu uuuu 1111 1111 1111 1111
PORTB TRISB OPTION
PORTB Data Direction Register T0CS T0SE
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
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PIC16F72
3.3 PORTC and the TRISC Register
FIGURE 3-5:
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some www..com peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select(1) Peripheral Data Out Data Bus WR Port 0
D CK Q Q
VDD P VDD
1
I/O pin
Data Latch WR TRIS
D CK Q Q
N VSS
VSS
TRIS Latch Schmitt Trigger
Q D EN
RD TRIS Peripheral OE(2) RD Port Peripheral Input
EXAMPLE 3-3:
BANKSEL CLRF PORTC PORTC
INITIALIZING PORTC
; ; ; ; ; ; ; ; ; ; ; Select Bank for PORTC Initialize PORTC by clearing output data latches Select Bank for TRISC Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs
Note 1: Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only activated if peripheral select is active.
BANKSEL MOVLW
TRISC 0xCF
MOVWF
TRISC
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TABLE 3-5:
Name RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO
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PORTC FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin or Timer1 oscillator input. Input/output port pin or Capture1 input/Compare1 output/PWM1 output. RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin. Input/output port pin.
RC6 RC7
Legend: ST = Schmitt Trigger input
TABLE 3-6:
Address Name 07h 87h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on POR, BOR Value on all other RESETS
PORTC TRISC
xxxx xxxx uuuu uuuu 1111 1111 1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged
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4.0 READING PROGRAM MEMORY
4.1 PMADR
The FLASH Program Memory is readable during normal operation over the entire VDD range. It is indirectly addressed through Special Function Registers (SFR). Up to 14-bit wide numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a NOP. There are five SFRs used to read the program and memory: * * www..com * * * PMCON1 PMDATL PMDATH PMADRL PMADRH The address registers can address up to a maximum of 8K words of program FLASH. When selecting a program address value, the MSByte of the address is written to the PMADRH register and the LSByte is written to the PMADRL register. The upper MSbits of PMADRH must always be clear.
4.2
PMCON1 Register
PMCON1 is the control register for memory accesses. The control bit RD initiates read operations. This bit cannot be cleared, only set, in software. It is cleared in hardware at the completion of the read operation.
The program memory allows word reads. Program memory access allows for checksum calculation and reading calibration tables. When interfacing to the program memory block, the PMDATH:PMDATL registers form a two-byte word, which holds the 14-bit data for reads. The PMADRH:PMADRL registers form a two-byte word, which holds the 13-bit address of the FLASH location being accessed. This device has up to 2K words of program FLASH, with an address range from 0h to 07FFh. The unused upper bits PMDATH<7:6> and PMADRH<7:5> are not implemented and read as zeros.
REGISTER 4-1:
PMCON1: PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS 18Ch)
R-1 reserved bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/S-0 RD bit 0
bit 7 bit 6-1 bit 0
Reserved: Read as `1' Unimplemented: Read as `0' RD: Read Control bit 1 = Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a FLASH read Legend: W = Writable bit R = Readable bit `1' = Bit is set U = Unimplemented bit, read as `0' S = Settable bit `0' = Bit is cleared -n = Value at POR x = Bit is unknown
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4.3 Reading the FLASH Program Memory 4.4 Operation During Code Protect
The FLASH program memory control can read anywhere within the program memory, whether or not the program memory is code protected. This does not compromise the code, because there is no way to rewrite a portion of the program memory, or leave contents of a program memory read in a register while changing modes.
To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers and then set control bit, RD (PMCON1<0>). Once the read control bit is set, the program memory FLASH controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the "BSF PMCON1,RD" instruction to be ignored. The data is available in the very next cycle in the PMDATL and PMDATH registers; therefore, it can be read as two bytes in the following instructions. PMDATL and PMDATH registers will hold this value until another www..com read, or until it is written to by the user (during a write operation).
EXAMPLE 4-1:
BANKSEL MOVLW MOVWF MOVLW MOVWF BANKSEL BSF NOP NOP
FLASH PROGRAM READ
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Select Bank for PMADRH MS Byte of Program Address to read LS Byte of Program Address to read Select Bank for PMCON1 EE Read Any instructions here are ignored as program memory is read in second cycle after BSF PMCON1,RD First instruction after BSF PMCON1,RD executes normally Select Bank for PMDATL W = LS Byte of Program PMDATL W = MS Byte of Program PMDATL
PMADRH MS_PROG_EE_ADDR PMADRH LS_PROG_EE_ADDR PMADRL PMCON1 PMCON1, RD
BANKSEL PMDATL MOVF PMDATL, W MOVF PMDATH, W
TABLE 4-1:
Address 10Dh 10Fh 10Ch 10Eh 18Ch
REGISTERS ASSOCIATED WITH PROGRAM FLASH
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS
PMADRL PMADRH PMDATL PMDATH PMCON1
Address Register Low Byte -- -- --(1) -- -- -- -- Address Register High Byte Data Register Low Byte Data Register High Byte -- -- -- -- -- RD
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1--- ---0 1--- ---0
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. Shaded cells are not used during FLASH access. Note 1: This bit always reads as a `1'.
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5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting bit T0CS (OPTION<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/ T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.3. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler is not readable or writable. Section 5.4 details the operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT.
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Additional information on the Timer0 module is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
5.2
Timer0 Interrupt
5.1
Timer0 Operation
Timer mode is selected by clearing bit T0CS (OPTION<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit TMR0IF (INTCON<2>). The interrupt can be masked by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF must be cleared in software by the Timer0 module Interrupt Service Routine, before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP.
FIGURE 5-1:
CLKO (= FOSC/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus M U X 8 1 0 M U X SYNC 2 Cycles TMR0 reg
0 1
RA4/T0CKI pin T0SE
T0CS
PSA PRESCALER
Set Flag bit TMR0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
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5.3 Using Timer0 with an External Clock
Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure 5-1). The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. Note: Writing to TMR0 when the prescaler is assigned to Timer0, will clear the prescaler count but will not change the prescaler assignment.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
5.4
Prescaler
www..com is only one prescaler available, which is mutually There
exclusively shared between the Timer0 module and the Watchdog Timer. A prescaler assignment for the
TABLE 5-1:
Address 01h,101h
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS
TMR0
Timer0 Module Register GIE PEIE TMR0IE INTE T0CS T0SE RBIE TMR0IF INTF PSA PS2 PS1
xxxx xxxx uuuu uuuu RBIF 0000 000x 0000 000u PS0 1111 1111 1111 1111
0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h
OPTION RBPU INTEDG
Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Timer0.
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6.0 TIMER1 MODULE
6.1 Timer1 Operation
The Timer1 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * RESET from CCP module trigger Timer1 has a control register, shown in Register 6-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>).
www..com Figure 6-2 is a simplified block diagram of the Timer1
Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The Operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer1 also has an internal "RESET input". This RESET can be generated by the CCP module (Section 8.0).
module. Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Reference Manual, (DS33023).
REGISTER 6-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 -- bit 7 U-0 -- R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 R/W-0 R/W-0 R/W-0 TMR1ON bit 0 T1OSCEN T1SYNC TMR1CS
bit 7-6 bit 5-4
Unimplemented: Read as `0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (The oscillator inverter is turned off to eliminate power drain.) T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = `0'. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3
bit 2
bit 1
bit 0
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6.2 Timer1 Operation in Timer Mode 6.4
Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect, since the internal clock is always in sync.
Timer1 Operation in Synchronized Counter Mode
6.3
Timer1 Counter Operation
Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared. If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter. In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. The prescaler, however, will continue to increment.
Timer1 may operate in Asynchronous or Synchronous mode, depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have www..com a falling edge before the counter begins to increment.
FIGURE 6-1:
T1CKI (Default High)
TIMER1 INCREMENTING EDGE
T1CKI (Default Low)
Note: Arrows indicate counter increments.
FIGURE 6-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0 1 TMR1ON On/Off T1SYNC
Synchronized Clock Input
T1OSC RC0/T1OSO/T1CKI
(2)
1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS
Synchronize det Q Clock
RC1/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
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6.5 Timer1 Operation in Asynchronous Counter Mode
TABLE 6-1:
Osc Type LP
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Freq 32 kHz 100 kHz 200 kHz C1 33 pF 15 pF 15 pF C2 33 pF 15 pF 15 pF
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, that will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.5.1). In Asynchronous Counter mode, Timer1 cannot be used as a time base for capture or compare operations.
These values are for design guidance only.
Note 1: Higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
6.5.1
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READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Data in the Timer1 register (TMR1) may become corrupted. Corruption occurs when the timer enable is turned off at the same instant that a ripple carry occurs in the timer module. Reading the 16-bit value requires some care. Examples 12-2 and 12-3 in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.
6.7
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/ clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
6.8
Resetting Timer1 Using a CCP Trigger Output
If the CCP module is configured in Compare mode to generate a "special event trigger" signal (CCP1M3:CCP1M0 = 1011), the signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
6.6
Timer1 Oscillator
A crystal oscillator circuit is built between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.
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6.9 Resetting Timer1 Register Pair (TMR1H, TMR1L) 6.10 Timer1 Prescaler
The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.
TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected.
TABLE 6-2:
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Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on POR, BOR Value on all other RESETS
Name
0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 0Eh 0Fh 10h Legend: PIR1 PIE1 TMR1L TMR1H T1CON
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding register for the Least Significant Byte of the 16-bit TMR1 Register Holding register for the Most Significant Byte of the 16-bit TMR1 Register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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7.0
* * * * * * *
TIMER2 MODULE
7.2
Timer2 Prescaler and Postscaler
The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift
The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device RESET (Power-on Reset, MCLR , WDT Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written.
7.3
Timer2 Interrupt
Timer2 has a control register, shown in Register 7-1. Timer2 can be shut-off by clearing control bit TMR2ON www..com (T2CON<2>) to minimize power consumption. Figure 7-1 is a simplified block diagram of the Timer2 module. Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Reference Manual, (DS33023).
The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET.
7.4
Output of TMR2
7.1
Timer2 Operation
The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate a shift clock.
Timer2 can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).
FIGURE 7-1:
Sets Flag bit TMR2IF TMR2 (1) Output RESET Postscaler 1:1 to 1:16 4
TIMER2 BLOCK DIAGRAM
TMR2 reg Comparator
Prescaler 1:1, 1:4, 1:16 2
FOSC/4
EQ
PR2 reg
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
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REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0 -- bit 7 bit 7 bit 6-3 Unimplemented: Read as `0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 TOUTPS1 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 TOUTPS3 TOUTPS2 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
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bit 2
bit 1-0
TABLE 7-1:
Address
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7 Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on POR, BOR Value on all other RESETS
Name
0Bh,8Bh, INTCON GIE 10Bh, 18Bh 0Ch 8Ch 11h 12h 92h Legend: PIR1 PIE1 TMR2 T2CON PR2 -- -- --
0000 000x 0000 000u
TMR1IF -0-- 0000 0000 0000 TMR1IE -0-- 0000 0000 0000
0000 0000 0000 0000
Timer2 Module Register Timer2 Period Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module.
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PIC16F72
8.0 CAPTURE/COMPARE/PWM (CCP) MODULE
Additional information on the CCP module is available in the PICmicroTM Mid-Range MCU Reference Manual, (DS33023).
The CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a: * 16-bit capture register * 16-bit compare register * PWM master/slave duty cycle register. Table 8-1 shows the timer resources of the CCP Module modes. Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls www..com the operation of CCP1. All are readable and writable.
TABLE 8-1:
CCP MODE - TIMER RESOURCE
Timer Resource Timer1 Timer1 Timer2
CCP Mode Capture Compare PWM
REGISTER 8-1:
CCPCON1: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h)
U-0 -- bit 7 U-0 -- R/W-0 CCPxX R/W-0 CCPxY R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0
bit 7-6 bit 5-4
Unimplemented: Read as '0' CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3-0
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8.1 Capture Mode
8.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
8.1.3
SOFTWARE INTERRUPT
An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured www..com value is overwritten by the new captured value.
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF, following any such change in Operating mode.
8.1.4
CCP PRESCALER
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition.
There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any RESET will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
FIGURE 8-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF (PIR1<2>)
EXAMPLE 8-1:
CCPR1L
Prescaler / 1, 4, 16 RC2/CCP1 pin
CHANGING BETWEEN CAPTURE PRESCALERS
CCPR1H and edge detect Capture Enable
CLRF MOVLW
MOVWF
TMR1H TMR1L
CCP1CON ; Turn CCP module off NEW_CAPT_PS ; Load the W reg with ; the new prescaler ; mode value and CCP ON CCP1CON ; Load CCP1CON with ; this value
CCP1CON<3:0> Q's
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8.2 Compare Mode
8.2.1 CCP PIN CONFIGURATION
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: * Driven High * Driven Low * Remains Unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. The output may become inverted when the mode of the module is changed from Compare/Clear on Match www..com (CCPxM<3:0> = `1001') to Compare/Set on Match (CCPxM<3:0> = `1000'). This may occur as a result of any operation that selectively clears bit CCPxM0, such as a BCF instruction. When this condition occurs, the output becomes inverted when the instruction is executed. It will remain inverted for all following Compare operations, until the module is reset. The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch.
8.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
8.2.3
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled).
8.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated that may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special trigger output of CCP1 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
FIGURE 8-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special event trigger will: * RESET Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>) * Set bit GO/DONE (ADCON0<2>) bit, which starts an A/D conversion Special Event Trigger Set Flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S Output Logic Match RC2/CCP1 R pin TRISC<2> Output Enable CCP1CON<3:0> Mode Select Comparator TMR1H TMR1L
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TABLE 8-2:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Name Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on POR, BOR Value on all other RESETS
0Bh,8Bh INTCON 10Bh,18Bh 0Ch 8Ch 87h 0Eh 0Fh 10h www..com 15h 16h 17h Legend: PIR1 PIE1 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON
0000 000x 0000 000u
TMR1IF -0-- 0000 0000 0000 TMR1IE -0-- 0000 0000 0000
1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
PORTC Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- -- CCP1X CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by Capture and Timer1.
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8.3 PWM Mode
8.3.1 PWM PERIOD
In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the formula in Equation 8-1.
EQUATION 8-1:
PWM PERIOD
PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 7.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode. For www..com a step by step procedure on how to set up the CCP module for PWM operation, see Section 8.3.3.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
CCPR1H (Slave)
8.3.2
Comparator R Q RC2/CCP1 TMR2 (Note 1) S TRISC<2> Clear Timer, CCP1 pin and latch D.C.
PWM DUTY CYCLE
Comparator
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. Equation 8-2 is used to calculate the PWM duty cycle in time.
PR2
EQUATION 8-2:
PWM DUTY CYCLE
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base.
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared.
A PWM output (Figure 8-4) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 8-4:
Period
PWM OUTPUT
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
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Maximum PWM resolution (bits) for a given PWM frequency is calculated using Equation 8-3.
8.3.3
SET-UP FOR PWM OPERATION
EQUATION 8-3:
PWM MAX RESOLUTION
FOSC log ( FPWM ) log(2) bits
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
PWM Maximum Resolution =
Note:
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
4. 5.
For a sample PWM period and duty cycle calculation, see the PICmicroTM Mid-Range MCU Reference www..com (DS33023). Manual
TABLE 8-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 0xFF 10 4 0xFF 10 1 0xFF 10 1 0x3F 8 1 0x1F 7 1 0x17 5.5
Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 8-4:
Address
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on POR, BOR Value on all other RESETS
Name
0Bh,8Bh INTCON 10Bh,18Bh 0Ch 8Ch 87h 11h 92h 12h 15h 16h 17h Legend: PIR1 PIE1 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON
0000 000x 0000 000u
TMR1IF -0-- 0000 0000 0000 TMR1IE -0-- 0000 0000 0000
1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111
PORTC Data Direction Register Timer2 Module Register Timer2 Module Period Register --
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- -- CCP1X CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by PWM and Timer2.
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9.0
9.1
SYNCHRONOUS SERIAL PORT (SSP) MODULE
SSP Module Overview
9.2
SPI Mode
and
This section contains register definitions operational characteristics of the SPI module.
The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C)
2 An www..com overview of I C operations and additional informa-
SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) RC5/SDO RC4/SDI/SDA RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) RA5/AN4/SS When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (IDLE state of SCK) Clock edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) * * * *
tion on the SSP module can be found in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023). Refer to Application Note AN578, "Use of the SSP Module in the I 2C Multi-Master Environment."
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REGISTER 9-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 SMP bit 7 bit 7 SMP: SPI Data Input Sample Phase bits SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire(R)) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I2 C mode: This bit must be maintained clear CKE: SPI Clock Edge Select bits (Figure 9-2, Figure 9-3, and Figure 9-4) SPI mode, CKP = 0: 1 = Data transmitted on rising edge of SCK (Microwire alternate) 0 = Data transmitted on falling edge of SCK SPI mode, CKP = 1: 1 = Data transmitted on falling edge of SCK (Microwire default) 0 = Data transmitted on rising edge of SCK I2 C mode: This bit must be maintained clear D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: STOP bit (I2C mode only) - This bit is cleared when the SSP module is disabled, or when the START bit is detected last. SSPEN is cleared. 1 = Indicates that a STOP bit has been detected last (this bit is `0' on RESET) 0 = STOP bit was not detected last S: START bit (I2C mode only) - This bit is cleared when the SSP module is disabled, or when the STOP bit is detected last. SSPEN is cleared. 1 = Indicates that a START bit has been detected last (this bit is `0' on RESET) 0 = START bit was not detected last R/W: Read/Write Information bit (I2C mode only) - This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or ACK bit. 1 = Read 0 = Write UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty Legend: R = Readable bit - n = Value at POR R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
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bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow SSPEN: Synchronous Serial Port Enable bit In SPI mode: 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. CKP: Clock Polarity Select bit In SPI mode: 1 = IDLE state for clock is a high level (Microwire(R) default) 0 = IDLE state for clock is a low level (Microwire alternate) In I2 C mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch - used to ensure data setup time) SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1011 = I2C firmware controlled Master mode (Slave IDLE) 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
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bit 5
bit 4
bit 3-0
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FIGURE 9-1: SSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPBUF reg Write
To enable the serial port, SSP enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: * SDI must have TRISC<4> set * SDO must have TRISC<5> cleared * SCK (Master mode) must have TRISC<3> cleared * SCK (Slave mode) must have TRISC<3> set * SS must have TRISA<5> set and ADCON must be configured such that RA5 is a digital I/O . Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD.
SSPSR reg RC4/SDI/SDA RC5/SDO www..com bit0 Shift Clock
SS Control Enable RA5/AN4/SS Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TRISC<3>
2: If the SPI is used in Slave mode with CKE = `1', then the SS pin control must be enabled.
TMR2 Output 2 Prescaler TCY 4, 16, 64
TABLE 9-1:
Address
REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS
0Bh,8Bh INTCON 10Bh,18Bh 0Ch 8Ch 87h 13h 14h 85h 94h PIR1 PIE1 TRISC SSPBUF SSPCON TRISA SSPSTAT
GIE -- --
PEIE ADIF ADIE
TMR0IE -- --
INTE -- --
RBIE SSPIF SSPIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000 CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000
1111 1111 1111 1111 xxxx xxxx uuuu uuuu
PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN -- -- -- -- CKP SSPM3 SSPM2 SSPM1
SSPM0 0000 0000 0000 0000
--11 1111 --11 1111
PORTA Data Direction Register D/A P S R/W UA BF
--00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the SSP in SPI mode.
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PIC16F72
FIGURE 9-2:
SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SPI MODE TIMING, MASTER MODE
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SDI (SMP = 0) bit7 SDI (SMP = 1) bit7 SSPIF bit0 bit0
FIGURE 9-3:
SS (optional)
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SCK (CKP = 0) SCK (CKP = 1)
SDO SDI (SMP = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7 SSPIF
bit0
FIGURE 9-4:
SS
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SCK (CKP = 0) SCK (CKP = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0) bit7 SSPIF bit0
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9.3 SSP I 2C Mode Operation
The SSP module in I 2C mode fully implements all slave functions, except general call support and provides interrupts on START and STOP bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the Standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The SSP module functions are enabled by setting SSP
www..com bit SSPEN (SSPCON<5>). Enable
Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. Additional information on SSP I2C operation may be found in the PICmicroTM Mid-Range MCU Reference Manual (DS33023).
9.3.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. Either or both of the following conditions will cause the SSP module not to give this ACK pulse. a) b) The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received.
FIGURE 9-5:
SSP BLOCK DIAGRAM (I2C MODE)
Internal Data Bus Read Write SSPBUF Reg Shift Clock SSPSR Reg
RC3/SCK/SCL
RC4/ SDI/ SDA
MSb
LSb Addr Match
Match Detect
SSPADD Reg START and STOP Bit Detect Set, RESET S, P Bits (SSPSTAT Reg)
In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 9-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the SSP module are shown in timing parameter #100 and parameter #101.
The SSP module has five registers for I2C operation: * * * * SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible * SSP Address Register (SSPADD) The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address), with START and STOP bit interrupts enabled * I 2C Slave mode (10-bit address), with START and STOP bit interrupts enabled * I 2C Firmware controlled Master operation, Slave is IDLE
9.3.1.1
Addressing
Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the eight bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated, if enabled) - on the falling edge of the ninth SCL pulse.
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In 10-bit Address mode, two address bytes need to be received by the slave device. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. 2.
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9.3.1.3
Transmission
3. 4. 5.
6. 7. 8. 9.
Receive first (high) byte of address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address, if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated START condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master device must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master device by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 9-7). An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave device, the slave logic is reset (resets SSPSTAT register) and the slave device then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin RC3/SCK/SCL should be enabled by setting bit CKP.
9.3.1.2
Reception
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then a no Acknowledge (ACK) pulse is given. An overflow condition is indicated if either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte.
TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes
Status Bits as Data Transfer is Received BF 0 1 1 SSPOV 0 0 1 SSPSR SSPBUF Yes No No Generate ACK Pulse Yes No No
0 1 No No Yes Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
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FIGURE 9-6: I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address R/W = 0 Receiving Data Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SDA
SCL
SSPIF (PIR1<3>)
Cleared in software
Bus Master terminates transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>)
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Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
FIGURE 9-7:
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK
SDA
A7
A6
A5
A4
A3
A2
SCL
S
1 2 Data is sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>) BF (SSPSTAT<0>)
Cleared in software
SSPBUF is written in software CKP (SSPCON<4>)
From SSP Interrupt Service Routine
Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)
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9.3.2 MASTER MODE OPERATION 9.3.3 MULTI-MASTER MODE OPERATION
Master mode operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle, based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is IDLE and both the S and P bits are clear. In Master mode operation, the SCL and SDA lines are manipulated in firmware by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So, when transmitting data, a `1' data bit must have the www..com TRISC<4> bit set (input) and a `0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): * START condition * STOP condition * Data transfer byte transmitted/received Master mode operation can be done with either the Slave mode IDLE (SSPM3:SSPM0 = 1011), or with the Slave mode active. When both Master mode operation and Slave modes are used, the software needs to differentiate the source(s) of the interrupt. For more information on Master mode operation, see AN554 - Software Implementation of I2C Bus Master. In Multi-Master mode operation, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle, based on the START and STOP conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is IDLE and both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the STOP condition occurs. In Multi-Master mode operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost: * Address Transfer * Data Transfer When the slave logic is enabled, the Slave device continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to retransfer the data at a later time. For more information on Multi-Master mode operation, see AN578 - Use of the SSP Module in the I2C Multi-Master Environment.
TABLE 9-3:
Address
REGISTERS ASSOCIATED WITH I2C OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR
0000 000x
Value on all other RESETS
0000 000u
0Bh, 8Bh, 10Bh,18Bh 0Ch 8Ch 13h 93h 14h 94h 87h
INTCON PIR1 PIE1
GIE -- --
PEIE ADIF ADIE
TMR0IE -- --
INTE -- --
RBIE
TMR0IF
INTF
RBIF
SSPIF CCP1IF TMR2IF TMR1IF SSPIE CCP1IE TMR2IE TMR1IE
-0-- 0000 -0-- 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 1111 1111
0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register SSPADD Synchronous Serial Port (I2C mode) Address Register SSPCON SSPSTAT TRISC WCOL SMP(1) SSPOV CKE(1) SSPEN D/A CKP P SSPM3 SSPM2 SSPM1 SSPM0 S R/W UA BF
PORTC Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by SSP module in SPI mode. Note 1: Maintain these bits clear in I2C mode.
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10.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The A/D module has three registers: * A/D Result Register * A/D Control Register 0 * A/D Control Register 1 ADRES ADCON0 ADCON1
The analog-to-digital (A/D) converter module has five inputs for the PIC16F72. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD) or the voltage level on the RA3/AN3/VREF pin. The A/D converter has a unique feature of being able to www..com operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D's internal RC oscillator.
A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted. The ADCON0 register, shown in Register 10-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 10-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or a digital I/O. For more information on use of the A/D Converter, see AN546 - Use of A/D Converter, or refer to the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
REGISTER 10-1:
ADCON0: A/D CONTROL REGISTER 0 (ADDRESS 1Fh)
R/W-0 ADCS1 bit 7 R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit 0
bit 7-6
ADCS<1:0>: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) CHS<2:0>: Analog Channel Select bits 000 = Channel 0, (RA0/AN0) 001 = Channel 1, (RA1/AN1) 010 = Channel 2, (RA2/AN2) 011 = Channel 3, (RA3/AN3) 100 = Channel 4, (RA5/AN4) GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) Unimplemented: Read as `0' ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5-3
bit 2
bit 1 bit 0
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REGISTER 10-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh)
U-0 -- bit 7 bit 7-3 bit 2-0 Unimplemented: Read as `0' PCFG<2:0>: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x A = Analog input RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D VREF VDD RA3 VDD RA3 VDD RA3 VDD U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0
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D = Digital I/O
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 10-1. The value in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 10.1. After this acquisition time has elapsed, the A/D conversion can be started.
The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins/voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
2.
3. 4. 5.
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FIGURE 10-1: A/D BLOCK DIAGRAM
CHS2:CHS0
100 VAIN (Input Voltage) 011 010 A/D Converter 001 RA1/AN1 000 RA0/AN0 RA2/AN2 RA5/AN4 RA3/AN3/VREF
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VREF (Reference Voltage)
VDD 000 or 010 or 100 001 or 011 or 101 PCFG2:PCFG0
FIGURE 10-2:
ANALOG INPUT MODEL
VDD VT = 0.6 V RIC 1 k Sampling Switch SS RSS CHOLD = DAC capacitance = 51.2 pF VSS Legend: CPIN = input capacitance = threshold voltage VT I leakage = leakage current at the pin due to various junctions = interconnect resistance RIC SS = sampling switch CHOLD = sample/hold capacitance (from DAC)
Rs
ANx
VA
CPIN 5 pF
VT = 0.6 V
I leakage 500 nA
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch ( k )
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10.1 A/D Acquisition Requirements 10.3 Configuring Analog Port Pins
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 10-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed), this acquisition must be done www..com before the conversion can be started. To calculate the minimum acquisition time, TACQ, see the PICmicroTM Mid-Range MCU Reference Manual, (DS33023). In general, however, given a max of 10 k and at a temperature of 100C, TACQ will be no more than 16 s. The ADCON1, and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS<2:0> bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins), may cause the input buffer to consume current out of the device specification.
10.2
Selecting the A/D Conversion Clock
10.4
Note:
A/D Conversions
The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.0 TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: * * * * 2 TOSC 8 TOSC 32 TOSC Internal RC oscillator (2 - 6 s)
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time as small as possible, but no less than 1.6 s and not greater than 6.4 s. Table 10-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2 TAD wait is required before the next acquisition is started. After this 2 TAD wait, an acquisition is automatically started on the selected channel. The GO/DONE bit can then be set to start the conversion.
TABLE 10-1:
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD) Maximum Device Frequency ADCS<1:0> 00 01 10 11 Max. 1.25 MHz 5 MHz 20 MHz (Note 1)
Operation 2 TOSC 8 TOSC 32 TOSC RC(1, 2)
Note 1: The RC source has a typical TAD time of 4 s, but can vary between 2-6 s. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for SLEEP operation.
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10.5 A/D Operation During SLEEP 10.6 Effects of a RESET
The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit. A device RESET forces all registers to their RESET state. The A/D module is disabled and any conversion in progress is aborted. All A/D input pins are configured as analog inputs. The ADRES register will contain unknown data after a Power-on Reset.
10.7
Use of the CCP Trigger
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An A/D conversion can be started by the "special event trigger" of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter.
TABLE 10-2:
Address
REGISTERS/BITS ASSOCIATED WITH A/D
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF Bit 0 RBIF Value on POR, BOR
0000 000x
Name
Value on all other RESETS
0000 000u -0-- 0000 -0-- 0000 uuuu uuuu 0000 00-0 ---- -000 --0u 0000 --11 1111
INTCON 0Bh,8Bh 10Bh,18Bh 0Ch 8Ch 1Eh 1Fh 9Fh 05h 85h PIR1 PIE1 ADRES
TMR2IF TMR1IF -0-- 0000 TMR2IE TMR1IE -0-- 0000
xxxx xxxx
A/D Result Register CHS2 -- RA5 CHS1 -- RA4 CHS0 GO/DONE -- RA3 PCFG2 RA2 -- PCFG1 RA1 ADON PCFG0 RA0
ADCON0 ADCS1 ADCS0 ADCON1 PORTA TRISA -- -- -- -- -- --
0000 00-0 ---- -000 --0x 0000 --11 1111
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used for A/D conversion.
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11.0 SPECIAL FEATURES OF THE CPU
SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. Configuration bits are used to select the desired oscillator mode. Additional information on special features is available in the PICmicroTM Mid-Range Reference Manual (DS33023).
These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving Operating modes and offer code protection: * Oscillator Selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) www..com * Interrupts * Watchdog Timer (WDT) * SLEEP * Code Protection * ID Locations * In-Circuit Serial Programming These devices have a Watchdog Timer, which can be enabled or disabled using a configuration bit. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in RESET while the power supply stabilizes, and is enabled or disabled using a configuration bit. With these two timers on-chip, most applications need no external RESET circuitry.
11.1
Configuration Bits
The configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space, which can be accessed only during programming.
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REGISTER 11-1:
U-1 -- bit13 bit 13-7 bit 6 Unimplemented: Read as `1' BOREN: Brown-out Reset Enable bit(2) 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `1' CP: FLASH Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code protected PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh. 2: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' u = Unchanged from programmed state - n = Value when device is unprogrammed U-1 -- U-1 --
CONFIGURATION WORD (ADDRESS 2007h)(1)
U-1 -- U-1 -- U-1 -- U-1 -- u-1 BOREN U-1 -- u-1 CP u-1 u-1 u-1 u-1 bit0 PWRTEN WDTEN F0SC1 F0SC0
bit 5 bit 4
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bit 3
bit 2
bit 1-0
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11.2
11.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 11-2:
EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION)
The PIC16F72 can be operated in four different Oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor
Clock from Ext. System Open
OSC1 PIC16F72 (HS Mode) OSC2
11.2.2
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CRYSTAL OSCILLATOR/CERAMIC RESONATORS
TABLE 11-1:
In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKI and OSC2/CLKO pins to establish oscillation (Figure 11-1). The PIC16F72 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in HS mode, the device can accept an external clock source to drive the OSC1/CLKI pin (Figure 11-2). See Figure 14-1 or Figure 14-2 (depending on the part number and VDD range) for valid external clock frequencies.
CERAMIC RESONATORS (FOR DESIGN GUIDANCE ONLY)
Typical Capacitor Values Used: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1 56 pF 47 pF 33 pF 27 pF 22 pF OSC2 56 pF 47 pF 33 pF 27 pF 22 pF
HS
Capacitor values are for design guidance only.
FIGURE 11-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 To internal logic SLEEP PIC16F72
These capacitors were tested with the resonators listed below for basic start-up and operation. These values were not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes at the bottom of page 62 for additional information.
C1(1)
XTAL OSC2 RS(2) C2(1)
RF(3)
Note 1: See Table 11-1 and Table 11-2 for typical values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen.
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TABLE 11-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR (FOR DESIGN GUIDANCE ONLY)
Crystal Freq 32 kHz 200 kHz XT 200 kHz 1 MHz 4 MHz HS www..com 4 MHz 8 MHz 20 MHz Typical Capacitor Values Tested: C1 LP 33 pF 15 pF 56 pF 15 pF 15 pF 15 pF 15 pF 15 pF C2 33 pF 15 pF 56 pF 15 pF 15 pF 15 pF 15 pF 15 pF
VDD REXT OSC1 CEXT VSS FOSC/4 Recommended values: OSC2/CLKO 3 k REXT 100 k CEXT > 20 pF Internal Clock PIC16F72
11.2.3
RC OSCILLATOR
Osc Type
For timing insensitive applications, the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 11-3 shows how the R/C combination is connected to the PIC16F72.
FIGURE 11-3:
RC OSCILLATOR MODE
Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values were not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Note 1: Higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
11.3
RESET
The PIC16F72 differentiates between various kinds of RESET: * * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR)
Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a "RESET state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different RESET situations, as indicated in Table 11-4. These bits are used in software to determine the nature of the RESET. See Table 11-6 for a full description of RESET states of all registers. A simplified block diagram of the on-chip RESET circuit is shown in Figure 11-4.
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PIC16F72
FIGURE 11-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External RESET MCLR SLEEP WDT Module VDD Rise Detect VDD Brown-out Reset Power-on Reset S WDT Time-out Reset
BOREN
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OST/PWRT OST 10-bit Ripple Counter OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple Counter R Q Chip_Reset
Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
11.4
MCLR
FIGURE 11-5:
VDD
PIC16F72 device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 11-5, is suggested.
RECOMMENDED MCLR CIRCUIT
PIC16F72
R1 1 k (or greater) MCLR C1 0.1 F (optional, not critical)
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PIC16F72
11.5 Power-on Reset (POR) 11.9 Time-out Sequence
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin to VDD, as described in Section 11.4. A maximum rise time for VDD is specified. See Section 14.0, Electrical Characteristics for details. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. For more information, see Application Note, AN607www..com Power-up Trouble Shooting (DS00607). On power-up, the time-out sequence is as follows: the PWRT delay starts (if enabled) when a POR occurs. Then, OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of RESET. If MCLR is kept low long enough, all delays will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16F72 device operating in parallel. Table 11-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 11-6 shows the RESET conditions for all the registers.
11.6
Power-up Timer (PWRT)
11.10 Power Control/Status Register (PCON)
The Power Control/Status Register, PCON, has two bits to indicate the type of RESET that last occurred. Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.
The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/ disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation. See DC parameters for details (TPWRT, parameter #33).
11.7
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024 oscillator cycles (from OSC1 input) delay after the PWRT delay is over (if enabled). This helps to ensure that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
11.8
Brown-out Reset (BOR)
The configuration bit, BOREN, can enable or disable the Brown-out Reset circuit. If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100 s), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a RESET may not occur. Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer then keeps the device in RESET for TPWRT (parameter #33, about 72 ms). If VDD should fall below VBOR during TPWRT, the Brown-out Reset process will restart when VDD rises above VBOR, with the Power-up Timer Reset. The Power-up Timer is always enabled when the Brown-out Reset circuit is enabled, regardless of the state of the PWRT configuration bit.
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PIC16F72
TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTEN = 0 72 ms + 1024 TOSC 72 ms PWRTEN = 1 1024 TOSC -- Brown-out 72 ms + 1024 TOSC 72 ms Wake-up from SLEEP 1024 TOSC -- Oscillator Configuration XT, HS, LP RC
TABLE 11-4:
STATUS BITS AND THEIR SIGNIFICANCE
Significance Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
BOR TO PD POR (PCON<1>) (PCON<0>) (STATUS<4>) (STATUS<3>) 0
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x x x 0 u u u u
1 0 x 1 0 0 u 1
1 x 0 1 1 0 u 0
0 0 u u u u u
TABLE 11-5:
RESET CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
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TABLE 11-6:
Register W INDF TMR0 PCL STATUS FSR PORTA PORTB
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INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset, Brown-out Reset xxxx xxxx N/A xxxx xxxx 0000h 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx xxxx xxxx ---0 0000 0000 000x -0-- 0000 xxxx xxxx xxxx xxxx --00 0000 0000 0000 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 -0-- 0000 ---- --qq 1111 1111 0000 0000 --00 0000 ---- -000 0--- 0000 xxxx xxxx xxxx xxxx xxxx xxxx 1--- ---0 MCLR Reset, WDT Reset uuuu uuuu N/A uuuu uuuu 0000h 000q quuu(3) uuuu uuuu --0u 0000 uuuu uuuu uuuu uuuu ---0 0000 0000 000u -0-- 0000 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 -000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 -0-- 0000 ---- --uu 1111 1111 0000 0000 --00 0000 ---- -000 0--- 0000 uuuu uuuu uuuu uuuu uuuu uuuu 1--- ---0 Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) -u-- uuuu(1) uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uu-u uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu -u-- uuuu ---- --uu 1111 1111 uuuu uuuu --uu uuuu ---- -uuu u--- uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1--- ---u
PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRES ADCON0 OPTION TRISA TRISB TRISC PIE1 PCON PR2 SSPADD SSPSTAT ADCON1 PMDATL PMADRL PMDATH PMADRH PMCON1
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear. Note 1: One or more bits in INTCON, PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 11-5 for RESET value for specific condition.
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PIC16F72
FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH PULL-UP RESISTOR)
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
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OST TIME-OUT
INTERNAL RESET
FIGURE 11-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 1
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 2
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
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PIC16F72
FIGURE 11-9: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)
5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT 0V 1V
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INTERNAL RESET
11.11 Interrupts
The PIC16F72 has up to eight sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, or the GIE bit.
The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the Special Function Register, PIR1. The corresponding interrupt enable bits are contained in Special Function Register, PIE1, and the peripheral interrupt enable bit is contained in Special Function Register INTCON. When an interrupt is serviced, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack, and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs, relative to the current Q cycle. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on RESET. The "return from interrupt" instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts.
FIGURE 11-10:
INTERRUPT LOGIC
TMR0IF TMR0IE Wake-up (If in SLEEP mode)
ADIF ADIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE TMR2IF TMR2IE
INTF INTE RBIF RBIE PEIE GIE
Interrupt to CPU
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PIC16F72
11.11.1 INT INTERRUPT 11.11.3 PORTB INTCON CHANGE
External interrupt on the RB0/INT pin is edge triggered, either rising, if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 11.14 for details on SLEEP www..com mode. An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>) (see Section 3.2).
11.12 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W, STATUS registers). This will have to be implemented in software, as shown in Example 11-1. For the PIC16F72 device, the register W_TEMP must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 20h in bank 0, it must also be defined at A0h in bank 1). The register STATUS_TEMP is only defined in bank 0.
11.11.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON<5>) (see Section 5.0).
EXAMPLE 11-1:
MOVWF SWAPF CLRF MOVWF : :(ISR) : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS, W AND PCLATH REGISTERS IN RAM
;Copy ;Swap ;bank ;Save W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register
W_TEMP STATUS,W STATUS STATUS_TEMP
;Insert user code here STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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11.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC oscillator that does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/ CLKO pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. www..com The WDT can be permanently disabled by clearing configuration bit WDTEN (see Section 11.1). WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION register. Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. 2: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
FIGURE 11-11:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 5-1) 0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX WDT Enable Bit PSA To TMR0 (Figure 5-1) 0 MUX 1 PSA PS2:PS0
WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION register.
TABLE 11-7:
Address 2007h 81h,181h
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 (1) RBPU Bit 6 BOREN(1) INTEDG Bit 5 -- T0CS Bit 4 CP T0SE Bit 3 Bit 2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0 PWRTEN(1) WDTEN PSA PS2
Config. bits OPTION
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 11-1 for operation of these bits.
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PIC16F72
11.14 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins www..com that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should also be considered. The MCLR pin must be at a logic high level (VIHMC). Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up occurs regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.
11.14.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
11.14.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or a peripheral interrupt.
External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of the device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred and caused wake-up. The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP Capture mode interrupt. Special event trigger (Timer1 in Asynchronous mode using an external clock). SSP (START/STOP) bit detect interrupt. SSP transmit or receive in Slave mode (SPI/I2C). A/D conversion (when A/D clock source is RC).
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FIGURE 11-12:
OSC1 CLKO(4) INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched www..com Instruction Executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2)
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Note
1: 2: 3: 4:
XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale) This delay will not be there for RC Osc mode. GIE = `1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = `0', execution will continue in-line. CLKO is not available in these Osc modes, but shown here for timing reference.
11.15 Program Verification/ Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes.
FIGURE 11-13:
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
11.16 ID Locations
Four memory locations (2000h - 2003h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the four Least Significant bits of the ID location are used.
External Connector Signals +5V 0V VPP CLK Data I/O
*
PIC16F72 VDD VSS MCLR/VPP RB6 RB7
11.17 In-Circuit Serial Programming
PIC16F72 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage (see Figure 11-13 for an example). This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For general information of serial programming, please refer to the In-Circuit Serial ProgrammingTM (ICSPTM) Guide (DS30277). For specific details on programming commands and operations for the PIC16F72 devices, please refer to the latest version of the PIC16F72 FLASH Program Memory Programming Specification (DS39588).
*
*
*
VDD
To Normal Connections
* Isolation devices (as required).
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PIC16F72
12.0 INSTRUCTION SET SUMMARY
Table 12-2 lists the instructions recognized by the MPASMTM assembler. Figure 12-1 shows the general formats that the instructions can have. All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. Each PIC16F72 instruction is a 14-bit word divided into an OPCODE that specifies the instruction type and one or more operands that further specify the operation of the instruction. The PIC16F72 instruction set summary in Table 12-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 12-1 shows the opcode field descriptions. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of www..com operation is to be placed. If `d' is zero, the result is the placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator which selects the number of the bit affected by the operation, while `f' represents the number of the file in which the bit is located. For literal and control operations, `k' represents an eight or eleven-bit constant or literal value.
FIGURE 12-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value
CALL and GOTO instructions only
0
TABLE 12-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
8
7 k (literal)
0
13
11 OPCODE
10 k (literal)
0
d
k = 11-bit immediate value
PC TO PD
A description of each instruction is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles, with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s.
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PIC16F72
TABLE 12-2:
Mnemonic, Operands
PIC16F72 INSTRUCTION SET
Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF www..com MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, b f, b f, b f, b k k k k k k k k k Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2 1,2 1,2 3 3
BIT-ORIENTED FILE REGISTER OPERATIONS
01 01 01 01 11 11 10 00 10 11 11 00 11 00 00 11 11 00bb 01bb 10bb 11bb 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 bfff bfff bfff bfff kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk ffff ffff ffff ffff kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
LITERAL AND CONTROL OPERATIONS C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Additional information on the mid-range instruction set is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
Note:
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12.1
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. Operation: Status Affected: Description: k ANDWF Syntax: Operands: AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' = `0', the result is stored in the W register. If `d' = `1', the result is stored back in register `f'. f,d
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ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' = `0', the result is stored in the W register. If `d' = `1', the result is stored back in register `f'. f,d
BCF Syntax: Operands: Operation: Status Affected: Description:
Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' = `0', the next instruction is executed. If bit `b' = `1', then the next instruction is discarded and a NOP is executed instead, making this a 2 TCY instruction. Status Affected: Description: CLRF Syntax: Operands: Operation: Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
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BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' = `1', the next instruction is executed. If bit `b' in register `f' = `0', the next instruction is discarded, and a NOP is executed instead, making this a 2 TCY instruction.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC) + 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
Status Affected: Description:
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COMF Syntax: Operands: Operation: Status Affected: Description: Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' = `0', the result is stored in W. If `d' = `1', the result is stored back in register `f'. Status Affected: Description: f,d GOTO Syntax: Operands: Operation: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
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DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' = `0', the result is stored in the W register. If `d' = `1', the result is stored back in register `f'.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' = `0', the result is placed in the W register. If `d' = `1', the result is placed back in register `f'.
DECFSZ Syntax: Operands: Operation: Status Affected: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' = `0', the result is placed in the W register. If `d' = `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2 TCY instruction.
INCFSZ Syntax: Operands: Operation: Status Affected: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' = `0', the result is placed in the W register. If `d' = `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2 TCY instruction.
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IORLW Syntax: Operands: Operation: Status Affected: Description: Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'd with the eight-bit literal `k'. The result is placed in the W register. MOVLW Syntax: Operands: Operation: Status Affected: Description: Move Literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The don't cares will assemble as `0's. MOVLW k 0 k 255
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IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' = `0', the result is placed in the W register. If `d' = `1', the result is placed back in register `f'.
MOVWF Syntax: Operands: Operation: Status Affected: Description:
Move W to f [ label ] (W) (f) None Move data from W register to register `f'. MOVWF f 0 f 127
MOVF Syntax: Operands: Operation: Status Affected: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are moved to a destination dependant upon the status of `d'. If `d' = `0', the destination is W register. If `d' = `1', the destination is file register `f' itself. `d' = `1' is useful to test a file register, since status flag Z is affected.
NOP Syntax: Operands: Operation: Status Affected: Description:
No Operation [ label ] None No operation None No operation. NOP
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RETFIE Syntax: Operands: Operation: Status Affected: Return from Interrupt [ label ] None TOS PC, 1 GIE None RETFIE RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry Flag. If `d' = `0', the result is placed in the W register. If `d' = `1', the result is stored back in register `f'.
C Register f
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RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry Flag. If `d' = `0', the result is placed in the W register. If `d' = `1', the result is placed back in register `f'.
C Register f
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. SLEEP
Status Affected: Description:
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SUBLW Syntax: Operands: Operation: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR Literal with W [ label ] XORLW k
0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
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SUBWF Syntax: Operands: Operation: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' = `0', the result is stored in the W register. If `d' = `1', the result is stored back in register `f'.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' = `0', the result is stored in the W register. If `d' = `1', the result is stored back in register `f'. f,d
Status Affected: C, DC, Z
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' = `0', the result is placed in W register. If `d' = `1', the result is placed in register `f'.
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13.0 DEVELOPMENT SUPPORT
The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator www..com * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board
13.2
MPASM Assembler
The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process.
13.1
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help
13.3
MPLAB C17 and MPLAB C18 C Compilers
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display.
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13.4 MPLINK Object Linker/ MPLIB Object Librarian 13.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different www..com applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted.
The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user.
13.7
ICEPIC In-Circuit Emulator
13.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool.
The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present.
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13.8 MPLAB ICD In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realwww..com time.
13.11 PICDEM 1 Low Cost PICmicro Demonstration Board
The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB.
13.9
PRO MATE II Universal Device Programmer
The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode.
13.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board
The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad.
13.10 PICSTART Plus Entry Level Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
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13.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may www..com also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
13.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware.
13.15 KEELOQ Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters.
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24CXX/ 25CXX/ 93CXX
PIC14000
HCSXXX
PIC16C5X
PIC16C6X
PIC16C7X
PIC17C4X
PIC16F62X
PIC16C8X/ PIC16F8X
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
PIC18FXXX
MCRFXXX
MCP2510
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TABLE 13-1:
MPLAB(R) Integrated Development Environment
9
9
9
9
9
9
9
9
9
9
9
9
9
99
99
MPLAB(R) C17 C Compiler
Software Tools
MPLAB(R) C18 C Compiler
MPASMTM Assembler/ MPLINKTM Object Linker
9
9
Programmers Debugger Emulators
Demo Boards and Eval Kits
2002 Microchip Technology Inc.
999
999
99
**
99
99
99
99
99
99
99
99
99
99
99
99
MPLAB(R) ICE In-Circuit Emulator
ICEPICTM In-Circuit Emulator
9
* *
9
9
9
9
9
9
9
MPLAB(R) ICD In-Circuit Debugger
9
**
9
9
9
PICSTART(R) Plus Entry Level Development Programmer
9
**
9
9
9
9
9
9
9
9
9
9
9
9
9
9
PRO MATE(R) II Universal Device Programmer
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
PICDEMTM 1 Demonstration Board
9

9
9
9
9
DEVELOPMENT TOOLS FROM MICROCHIP
PICDEMTM 2 Demonstration Board
9
9
9
9
PICDEMTM 3 Demonstration Board
9
PICDEMTM 14A Demonstration Board
9
PICDEMTM 17 Demonstration Board
9
KEELOQ(R) Evaluation Kit
99
KEELOQ(R) Transponder Kit
microIDTM Programmer's Kit
99
125 kHz microIDTM Developer's Kit
125 kHz Anticollision microIDTM Developer's Kit
9
13.56 MHz Anticollision microIDTM Developer's Kit
9
PIC16F72
DS39597B-page 85
MCP2510 CAN Developer's Kit
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices.
9
PIC16F72
NOTES:
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DS39597B-page 86
2002 Microchip Technology Inc.
PIC16F72
14.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Ambient temperature under bias................................................................................................................ -55 to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V Voltage on MCLR with respect to VSS (Note 2) ..............................................................................................0 to +13.5V Voltage on RA4 with respect to Vss ...................................................................................................................0 to +12V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA
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Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA, PORTB..........................................................................................................200 mA Maximum current sourced by PORTA, PORTB ....................................................................................................200 mA Maximum current sunk by PORTC .......................................................................................................................200 mA Maximum current sourced by PORTC ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) 2: Voltage spikes at the MCLR pin may cause unpredictable results. A series resistor of greater than 1 k should be used to pull MCLR to VDD, rather than tying the pin directly to VDD. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2002 Microchip Technology Inc.
DS39597B-page 87
PIC16F72
FIGURE 14-1: PIC16F72 (INDUSTRIAL, EXTENDED) VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V
Voltage
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4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
16 MHz
20 MHz
Frequency
FIGURE 14-2:
PIC16LF72 (INDUSTRIAL) VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
4 MHz
10 MHz
Frequency
FMAX = (12 MHz/V) (VDDAPPMIN - 2.5V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application. Note 2: FMAX has a maximum frequency of 10 MHz.
DS39597B-page 88
2002 Microchip Technology Inc.
PIC16F72
14.1 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
PIC16LF72 (Industrial) PIC16F72 (Industrial, Extended) Param No. D001
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Sym VDD
Characteristic Supply Voltage PIC16LF72
2.0 2.5 2.2 4.0 VBOR* -- --
-- -- -- -- -- 1.5 VSS
5.5 5.5 5.5 5.5 5.5 -- --
V V V V V V V
A/D not used, -40C to +85C A/D in use, -40C to +85C A/D in use, 0C to +85C All configurations BOR enabled (Note 7)
D001 D001A D002* D003 VDR VPOR
PIC16F72 RAM Data Retention Voltage (Note 1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage
See section on Power-on Reset for details
D004*
SVDD
0.05
--
--
V/ms See section on Power-on Reset for details
D005 * Note 1: 2:
VBOR
3.65
4.0
4.35
V
BOREN bit in configuration word enabled
3: 4: 5: 6: 7:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2002 Microchip Technology Inc.
DS39597B-page 89
PIC16F72
14.1 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
PIC16LF72 (Industrial) PIC16F72 (Industrial, Extended) Param No. D010
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Sym IDD
Characteristic Supply Current (Notes 2, 5) PIC16LF72
-- --
0.4 25 0.9 5.2 25
2.0 48 4 15 200
mA A mA mA A
D010A D010 D013 PIC16F72
XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc configuration FOSC = 20 MHz, VDD = 5.5V BOR enabled, VDD = 5.0V
--
D015*
IBOR Brown-out Reset Current (Note 6) IPD PIC16LF72 PIC16F72 IBOR Brown-out Reset Current (Note 6) *
--
Power-down Current (Notes 3, 5) -- -- -- -- 2.0 0.1 5.0 0.1 25 30 5 42 19 200 A A A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +85C BOR enabled, VDD = 5.0V
D020 D021 D020 D021 D023*
Note 1: 2:
3: 4: 5: 6: 7:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS39597B-page 90
2002 Microchip Technology Inc.
PIC16F72
14.2 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC Specification, Section 14.1. Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT and LP mode) OSC1 (in HS mode) Input High Voltage I/O ports with TTL buffer with Schmitt Trigger buffer Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No.
Sym VIL
D030 D030A www..com D031 D032 D033 VIH D040 D040A D041 D042 D042A D043 D070 D060 D061 D063 *
VSS VSS VSS VSS VSS VSS
-- -- -- -- -- --
0.15 VDD 0.8V 0.2 VDD 0.2 VDD 0.3V 0.3 VDD
V V V V V V
For entire VDD range 4.5V VDD 5.5V
(Note 1) (Note 1)
2.0 0.25 VDD + 0.8V 0.8 VDD
-- -- -- -- -- -- -- 250 -- -- --
VDD VDD VDD VDD VDD VDD VDD 400 1 5 5
V V V V V V V A A A A
4.5V VDD 5.5V For entire VDD range For entire VDD range (Note 1) (Note 1) VDD = 5V, VPIN = VSS Vss VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration
IPURB IIL
MCLR 0.8 VDD OSC1 (in XT and LP mode) 1.6V OSC1 (in HS mode) 0.7 VDD OSC1 (in RC mode) 0.9 VDD PORTB Weak Pull-up Current 50 Input Leakage Current (Notes 2, 3) I/O ports -- MCLR, RA4/T0CKI OSC1 -- --
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F72 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
2002 Microchip Technology Inc.
DS39597B-page 91
PIC16F72
14.2 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC Specification, Section 14.1. Characteristic Output Low Voltage I/O ports OSC2/CLKO (RC osc config) VOH D090 D092 D150* D100 VOD Output High Voltage I/O ports (Note 3) OSC2/CLKO (RC osc config) Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No. D080
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Sym VOL
-- --
-- --
0.6 0.6
V V
D083
IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1
VDD - 0.7 VDD - 0.7
-- -- -- --
-- -- 12 15
V V V pF
Open Drain High Voltage -- Capacitive Loading Specs on Output Pins COSC2 OSC2 pin --
D101 D102
CIO CB
All I/O pins and OSC2 (in RC mode)
--
--
50
pF
-- -- 400 pF SCL, SDA in I2C mode Program FLASH Memory D130 EP Endurance 100 1000 -- E/W 25C at 5V D131 VPR VDD for read 2.0 -- 5.5 V * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F72 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
DS39597B-page 92
2002 Microchip Technology Inc.
PIC16F72
14.3 Timing Parameter Symbology
(I2C specifications only) (I2C specifications only) Time The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS www..com di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free T 3. TCC:ST 4. Ts
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid Hi-impedance High Low
TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition
SU STO
Setup STOP condition
FIGURE 14-3:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2 for OSC2 output
2002 Microchip Technology Inc.
DS39597B-page 93
PIC16F72
FIGURE 14-4: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKO 3 3 4 4
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TABLE 14-1:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Symbol Characteristic External CLKI Frequency (Note 1) Min DC DC DC Oscillator Frequency (Note 1) DC 0.1 4 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCY -- -- -- -- -- -- Max 1 20 32 4 4 20 200 -- -- -- -- 10,000 250 -- DC -- -- -- 25 50 15 Units Conditions
FOSC
MHz XT Osc mode MHz HS Osc mode kHz LP Osc mode MHz RC osc mode MHz XT Osc mode MHz HS Osc mode kHz LP Osc mode ns ns ms ns ns ns ms ns ns ms ns ns ns ns XT Osc mode HS Osc mode LP Osc mode RC Osc mode XT Osc mode HS Osc mode LP Osc mode TCY = 4/FOSC XT oscillator LP oscillator HS oscillator XT oscillator LP oscillator HS oscillator
1
TOSC
External CLKI Period (Note 1)
1000 50 5 250 250 50 5
Oscillator Period (Note 1)
2 3
TCY TosL, TosH
Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time
200 500 2.5 15 -- -- --
4
TosR, TosF
External Clock in (OSC1) Rise or Fall Time
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
DS39597B-page 94
2002 Microchip Technology Inc.
PIC16F72
FIGURE 14-5: CLKO AND I/O TIMING
Q4 OSC1 10 CLKO 13 14 I/O Pin (Input) 19 18 12 16 11 Q1 Q2 Q3
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17 I/O Pin (Output) Old Value
15 New Value
20, 21 Note: Refer to Figure 14-3 for load conditions.
TABLE 14-2:
Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* Symbol TosH2ckL TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI
CLKO AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKO CLKO rise time CLKO fall time CLKO to Port out valid Port in valid before CLKO Port in hold after CLKO OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time Standard (F) Extended (LF) Min -- -- -- -- -- TOSC + 200 0 -- 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 100 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5 TCY + 20 -- -- 255 -- -- -- 40 145 40 145 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckH OSC1 to CLKO
19* 20* 21* 22* 23* *
TioV2osH TioR TioF TINP TRBP
Port input valid to OSC1 (I/O in setup time) Standard (F) Extended (LF) Standard (F) Extended (LF)
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
2002 Microchip Technology Inc.
DS39597B-page 95
PIC16F72
FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out 32 30
www..com OSC Time-out
Internal RESET Watchdog Timer Reset 34 I/O Pins Note: Refer to Figure 14-3 for load conditions.
31 34
FIGURE 14-7:
BROWN-OUT RESET TIMING
VDD
VBOR 35
TABLE 14-3:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Min 2 7 -- 28 -- 100 Typ -- 18 1024 TOSC 72 -- -- Max -- 33 -- 132 2.1 -- Units
s
Parameter No. Symbol 30 31* 32 33* 34 35 TmcL TWDT TOST TPWRT TIOZ TBOR
Conditions VDD = 5V, -40C to +85C VDD = 5V, -40C to +85C TOSC = OSC1 period VDD = 5V, -40C to +85C
ms -- ms
s s
VDD VBOR (D005)
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS39597B-page 96
2002 Microchip Technology Inc.
PIC16F72
FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
40
41
42
RC0/T1OSO/T1CKI
45
46
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47 TMR0 or TMR1 Note: Refer to Figure 14-3 for load conditions. 48
TABLE 14-4:
Param No. 40* 41* 42* Symbol Tt0H Tt0L Tt0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 25 30 50 0.5 TCY + 20 15 25 30 50 Greater of: 30 or TCY + 40 N Greater of: 50 or TCY + 40 N 60 100 DC 2 TOSC -- -- -- -- -- -- 200 7 TOSC ns ns kHz -- Typ -- -- -- -- -- -- Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Conditions Must also meet parameter 42 Must also meet parameter 42
45*
Tt1H
T1CKI High Time Synchronous, Prescaler = 1 Synchronous, Standard(F) Prescaler = 2,4,8 Extended(LF) Asynchronous Standard(F) Extended(LF)
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns
46*
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1 Synchronous, Standard(F) Prescaler = 2,4,8 Extended(LF) Asynchronous Standard(F) Extended(LF) Standard(F)
Must also meet parameter 47
47*
Tt1P
T1CKI Input Period
Synchronous
N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8)
Extended(LF)
Asynchronous Ft1 48 *
Standard(F) Extended(LF)
Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from External Clock Edge to Timer Increment
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
2002 Microchip Technology Inc.
DS39597B-page 97
PIC16F72
FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 )
RC2/CCP1 (Capture Mode)
50 52
51
RC2/CCP1 (Compare or PWM Mode)
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53 Note: Refer to Figure 14-3 for load conditions.
54
TABLE 14-5:
Param Symbol No. 50* TccL
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Characteristic CCP1 input low time No Prescaler With Prescaler Standard(F) Extended(LF) Min 0.5 TCY + 20 10 20 0.5 TCY + 20 10 20 3 TCY + 40 N Standard(F) Extended(LF) Standard(F) Extended(LF) -- -- -- -- Typ Max Units -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 50 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4 or 16) Conditions
51*
TccH
CCP1 input high No Prescaler time Standard(F) With Prescaler Extended(LF) CCP1 input period CCP1 output rise time CCP1 output fall time
52* 53* 54* *
TccP TccR TccF
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS39597B-page 98
2002 Microchip Technology Inc.
PIC16F72
FIGURE 14-10:
SS 70 SCK (CKP = 0) 71 72
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
78
79
SCK (CKP = 1) 79 78
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SDO
80 MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 14-3 for load conditions. Bit6 - - - -1 Bit6 - - - - - -1
LSb
LSb In
FIGURE 14-11:
SS
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
SDO
MSb 75, 76
Bit6 - - - - - -1
LSb
SDI
MSb In 74
Bit6 - - - -1
LSb In
Note: Refer to Figure 14-3 for load conditions.
2002 Microchip Technology Inc.
DS39597B-page 99
PIC16F72
FIGURE 14-12: SPI SLAVE MODE TIMING (CKE = 0)
SS 70 SCK (CKP = 0) 71 72 83
78
79
SCK (CKP = 1)
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80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 14-3 for load conditions. Bit6 - - - -1 Bit6 - - - - - -1
79
78
LSb 77 LSb In
FIGURE 14-13:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
Bit6 - - - - - -1
LSb 77
SDI
MSb In 74
Bit6 - - - -1
LSb In
Note: Refer to Figure 14-3 for load conditions.
DS39597B-page 100
2002 Microchip Technology Inc.
PIC16F72
TABLE 14-6:
Param No. 70* 71* 72* 73* 74*
www..com 75*
SPI MODE REQUIREMENTS
Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Setup time of SDI data input to SCK edge Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) Standard(F) Extended(LF) Standard(F) Extended(LF) Standard(F) Extended(LF) Min TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- -- -- TCY -- 1.5 TCY + 40 Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- Max Units Conditions -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF
76* 77* 78* 79* 80* 81* 82* 83* *
SCK output fall time (Master mode)
TscH2doV, SDO data output valid after TscL2doV SCK edge
TdoV2scH, SDO data output setup to SCK edge TdoV2scL TssL2doV SDO data output valid after SS edge TscH2ssH, SS after SCK edge TscL2ssH
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 14-14:
I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition Note: Refer to Figure 14-3 for load conditions.
STOP Condition
2002 Microchip Technology Inc.
DS39597B-page 101
PIC16F72
TABLE 14-7:
Param No. 90* 91* 92* 93
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I2C BUS START/STOP BITS REQUIREMENTS
Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min Typ Max Units 4700 600 4000 600 4700 600 4000 600 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated
Symbol TSU:STA THD:STA TSU:STO THD:STO
*
These parameters are characterized but not tested.
FIGURE 14-15:
I2C BUS DATA TIMING
103 100 101 102
SCL
90 91
106
107 92
SDA In 110 109 SDA Out Note: Refer to Figure 14-3 for load conditions. 109
DS39597B-page 102
2002 Microchip Technology Inc.
PIC16F72
TABLE 14-8:
Param No. 100*
I2C BUS DATA REQUIREMENTS
Characteristic Clock High Time 100 kHz mode 400 kHz mode SSP Module Min 4.0 0.6 1.5 TCY 4.7 1.3 1.5 TCY -- 20 + 0.1 CB -- 20 + 0.1 CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10 - 400 pF Only relevant for Repeated START condition After this period, the first clock pulse is generated CB is specified to be from 10 - 400 pF s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Units s s Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
Symbol THIGH
101*
TLOW
Clock Low Time
100 kHz mode 400 kHz mode
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SSP Module 102* TR SDA and SCL Rise 100 kHz mode Time 400 kHz mode SDA and SCL Fall Time START Condition Setup Time START Condition Hold Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Output Valid from Clock Bus Free Time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode CB Bus Capacitive Loading
103*
TF
90*
TSU:STA
91* 106* 107* 92* 109* 110*
THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
* These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.
2002 Microchip Technology Inc.
DS39597B-page 103
PIC16F72
TABLE 14-9:
Param No. A01
A/D CONVERTER CHARACTERISTICS: PIC16F72 (INDUSTRIAL) PIC16LF72 (INDUSTRIAL)
Characteristic Resolution PIC16F72 PIC16LF72 Min -- -- -- -- -- -- -- -- 2.5 2.2 VSS - 0.3 -- -- -- N/A -- Typ -- -- -- -- -- -- -- guaranteed -- -- -- -- 180 90 -- -- Max 8 bits 8 bits <1 <1 <1 <1 <1 -- VDD+0.3 VDD+0.3 VREF + 0.3 10.0 -- -- 5 500 Units bit bit Conditions VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 2.2V
Sym NR
A02 A03 A04 A05 A06 A10 A20 A25 A30 A40
EABS EIL EDL EFS EOFF -- VREF VAIN ZAIN IAD
Total Absolute Error Integral Linearity Error Differential Linearity Error Full Scale Error Offset Error Monotonicity (Note 3) Reference Voltage Analog Input Voltage Recommended Impedance of Analog Voltage Source A/D Conversion PIC16F72 Current (VDD) PIC16LF72 VREF input current (Note 2)
LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF -- V V V k A A A A Average current consumption when A/D is on (Note 1). During VAIN acquisition. During A/D Conversion cycle. VSS VAIN VREF -40C to +85C 0C to +85C
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A50
IREF
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
*
DS39597B-page 104
2002 Microchip Technology Inc.
PIC16F72
FIGURE 14-16: A/D CONVERSION TIMING
1 TCY (TOSC/2)(1) 131 130 A/D CLK 132 BSF ADCON0, GO 134 Q4
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
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ADIF GO SAMPLING STOPPED DONE
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 14-10: A/D CONVERSION REQUIREMENTS
Param Sym No. 130 TAD Characteristic A/D Clock Period PIC16F72 PIC16LF72 PIC16F72 PIC16LF72 131 132 TCNV Conversion Time (not including S/H time) (Note 1) Min 1.6 2.0 2.0 3.0 9 5* Typ Max Units -- -- 4.0 6.0 -- -- -- -- 6.0 9.0 9 -- s s s s TAD s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 3.0V TOSC based, 2.0V VREF 5.5V A/D RC mode A/D RC mode
TACQ Acquisition Time
134
TGO
Q4 to A/D Clock Start
--
TOSC/2 --
--
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle.
*
2002 Microchip Technology Inc.
DS39597B-page 105
PIC16F72
NOTES:
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DS39597B-page 106
2002 Microchip Technology Inc.
PIC16F72
15.0
Note:
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 15-1:
6
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
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5
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5 V
5.0 V 4 4.5 V IDD (mA) 4.0 V
3
2 3.5 V 3.0 V 1 2.5 V 2.0 V 0 4 6 8 10 12 F O S C (M H z ) 14 16 18 20
FIGURE 15-2:
8
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
7
6
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5 .5 V 5 .0 V 4 .5 V
5 IDD (mA)
4
4 .0 V
3
2
3 .5 V 3 .0 V
1 2 .5 V 2 .0 V 0 4 6 8 10 12 F O S C (M H z ) 14 16 18 20
2002 Microchip Technology Inc.
DS39597B-page 107
PIC16F72
FIGURE 15-3:
0.9
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
0.8
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
0.7 5.0V 0.6 4.5V IDD (mA) 0.5 4.0V 3.5V 3.0V 0.3 2.5V 2.0V 0.2
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0.4
0.1
0.0 0.0 0.5 1.0 1.5 2.0 FOSC (MHz) 2.5 3.0 3.5 4.0
FIGURE 15-4:
1.2
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
1.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
0.8
5.0V
4.5V IDD (mA) 0.6 4.0V 3.5V 0.4 3.0V 2.5V 2.0V 0.2
0.0 0.0 0.5 1.0 1.5 2.0 FOSC (MHz) 2.5 3.0 3.5 4.0
DS39597B-page 108
2002 Microchip Technology Inc.
PIC16F72
FIGURE 15-5:
55
TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
50
45
5.5V
40
5.0V
IDD (A)
35
4.5V 4.0V 3.5V
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30
25 3.0V 20 2.5V 2.0V
15
10 30 40 50 60 FOSC (kHz) 70 80 90 100
FIGURE 15-6:
100
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
90
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
5.5V
80 5.0V 70 4.5V IDD (A) 60 4.0V 50 3.5V 40 3.0V 2.5V 30 2.0V 20 30
40
50
60 FOSC (kHz)
70
80
90
100
2002 Microchip Technology Inc.
DS39597B-page 109
PIC16F72
FIGURE 15-7:
5.0
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, 25C)
4.5
Operation above 4 MHz is not recomended
4.0
3.5 10 k 3.0 Freq (MHz)
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2.0
1.5
1.0 100 k 0.5
0.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
FIGURE 15-8:
5.0
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, 25C)
Operation above 4 MHz is not recomended
4.0 5.1 k
3.0 Freq (MHz)
10 k 2.0
1.0
100 k 0.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
DS39597B-page 110
2002 Microchip Technology Inc.
PIC16F72
FIGURE 15-9:
300
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, 25C)
250 3.3 k
200 5.1 k Freq (kHz)
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150
10 k 100
50 100 k 0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
FIGURE 15-10:
100
IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Max 125C
10 Max 85C
IPD (uA)
1
Typ 25C 0.1
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
0.01 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
2002 Microchip Technology Inc.
DS39597B-page 111
PIC16F72
FIGURE 15-11:
1,000
IBOR vs. VDD OVER TEMPERATURE
Max (125C)
Typ (25C) Indeterminant State Device in SLEEP
IDD (A)
Device in RESET 100
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Note:
Device current in RESET depends on Oscillator mode, frequency and circuit.
Max (125C)
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
Typ (25C)
10 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 15-12:
100
TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
Max (125C) 10
IWDT (A)
Typ (25C)
1
0.1 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS39597B-page 112
2002 Microchip Technology Inc.
PIC16F72
FIGURE 15-13:
50
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C)
45
40
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
35 Max (125C) WDT Period (ms) 30
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25 Typ (25C)
20
15
Min (-40C)
10
5
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 15-14:
50
AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40C TO +125C)
45
40 125C 35 85C WDT Period (ms) 30 25C 25
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
20 -40C 15
10
5
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
2002 Microchip Technology Inc.
DS39597B-page 113
PIC16F72
FIGURE 15-15:
5.5 5.0 4.5 4.0 Max 3.5 Typ (25C) VOH (V) 3.0
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C)
www..com2.5
Min 2.0 1.5 1.0 0.5 0.0 0 5 10 IOH (-mA) 15 20 25
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
FIGURE 15-16:
3.5
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C)
3.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
2.5 Max
2.0 VOH (V) Typ (25C) 1.5 Min 1.0
0.5
0.0 0 5 10 IOH (-mA) 15 20 25
DS39597B-page 114
2002 Microchip Technology Inc.
PIC16F72
FIGURE 15-17:
1.0
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C)
0.9 Max (125C) 0.8
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
0.7 Max (85C)
0.6 VOL (V)
0.5 Typ (25C) 0.4
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0.3
Min (-40C)
0.2
0.1
0.0 0 5 10 IOL (-mA) 15 20 25
FIGURE 15-18:
3.0
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C)
Max (125C) 2.5
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
2.0
VOL (V)
1.5 Max (85C)
1.0 Typ (25C)
0.5
Min (-40C)
0.0 0 5 10 IOL (-mA) 15 20 25
2002 Microchip Technology Inc.
DS39597B-page 115
PIC16F72
FIGURE 15-19:
1.5
MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO +125C)
1.4
1.3
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
VTH Max (-40C)
1.2
1.1 VTH Typ (25C) VIN (V) 1.0
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0.9 VTH Min (125C)
0.8
0.7
0.6
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 15-20:
4.0
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)
3.5
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to +125C) Minimum: mean - 3 (-40C to +125C)
VIH Max (125C)
3.0
2.5
VIN (V)
VIH Min (-40C)
2.0
VIL Max (-40C)
1.5
1.0
VIL Min (125C)
0.5
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS39597B-page 116
2002 Microchip Technology Inc.
PIC16F72
16.0 PACKAGE MARKING INFORMATION
28-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F72-I/SP 0217017
28-Lead SOIC
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F72-I/SO
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0210017
28-Lead SSOP
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC16F72 -I/SS 0220017
28-Lead QFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
1
PIC16F72 -I/ML 0210017
1
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2002 Microchip Technology Inc.
DS39597B-page 117
PIC16F72
28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP)
E1
D
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2 n 1
E
A2 A L A1 B1 B p
c
eB
Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
INCHES* MIN NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 5 5 .310 .285 1.365 .130 .012 .053 .019 .350 10 10 .325 .295 1.385 .135 .015 .065 .022 .430 15 15 .150 .130 .160 .135 MAX MIN
MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 5 5 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 10 10 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 15 15 3.81 3.30 4.06 3.43 MAX
* Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095
Drawing No. C04-070
DS39597B-page 118
2002 Microchip Technology Inc.
PIC16F72
28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E E1 p
D
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B n h 45 c A

2 1
A2
L Units Dimension Limits n p A A2 A1 E E1 D h L c B
A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0
.104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15
2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052
2002 Microchip Technology Inc.
DS39597B-page 119
PIC16F72
28-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
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B n 2 1
A c A2

A1
L
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .396 .022 .004 0 .010 0 0
INCHES NOM 28 .026 .073 .068 .006 .309 .207 .402 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .319 .212 .407 .037 .010 8 .015 10 10
MILLIMETERS* NOM MAX 28 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0.38 0 5 10 0 5 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073
DS39597B-page 120
2002 Microchip Technology Inc.
PIC16F72
28-Lead Plastic Quad Flat No Leads Package (ML) 6x6 mm Body (QFN)
E E1 EXPOSED METAL PADS
Q D1 D D2 p 2
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1
B
n R CH x 45 TOP VIEW
E2 L BOTTOM VIEW
A2 A1 A3 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Width Molded Package Width Exposed Pad Width Overall Length Molded Package Length Exposed Pad Length Lead Width Lead Length Tie Bar Width Tie Bar Length Chamfer Mold Draft Angle Top n p A A2 A1 A3 E E1 E2 D D1 D2 B L R Q CH .140 .009 .020 .005 .012 .009 .140 .000 MIN
A
INCHES NOM 28 .026 BSC .033 .026 .0004 .008 REF. .236 BSC .226 BSC .146 .236 BSC .226 BSC .146 .011 .024 .007 .016 .017 .152 .014 .030 .010 .026 .024 12 .152 .039 .031 .002 MAX MIN
MILLIMETERS* NOM 28 0.65 BSC 0.85 0.65 0.00 0.01 0.20 REF. 6.00 BSC 5.75 BSC 3.55 3.70 6.00 BSC 5.75 BSC 3.55 0.23 0.50 0.13 0.30 0.24 3.70 0.28 0.60 0.17 0.40 0.42 3.85 0.35 0.75 0.23 0.65 0.60 12 3.85 1.00 0.80 0.05 MAX
* Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: pending Drawing No. C04-114
2002 Microchip Technology Inc.
DS39597B-page 121
PIC16F72
28-Lead Plastic Quad Flat No Leads Package (ML) 6x6 mm Body (QFN) (Continued)
M
B
L M
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p
SOLDER MASK
PACKAGE EDGE
Units Pitch Pad Width Pad Length Pad to Solder Mask *Controlling Parameter Drawing No. C04-2114 Dimension Limits p B L M MIN .009 .020 .005
INCHES NOM .026 BSC .011 .024 .014 .030 .006 MAX MIN
MILLIMETERS* NOM 0.65 BSC 0.23 0.50 0.13 0.28 0.60 0.35 0.75 0.15 MAX
DS39597B-page 122
2002 Microchip Technology Inc.
PIC16F72
APPENDIX A:
Version A
REVISION HISTORY
Date April 2002 Revision Description This is a new data sheet. However, this device is similar to the PIC16C72 device found in the PIC16C7X Data Sheet (DS30390), the PIC16C72A Data Sheet (DS35008) or the PIC16F872 device (DS30221). Final data sheet. Includes device characterization data. Minor typographic revisions throughout.
B
May 2002
APPENDIX B:
CONVERSION CONSIDERATIONS
www..com Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table B-1.
TABLE B-1:
CONVERSION CONSIDERATIONS
PIC16C72/72A 28 3 8 Basic SSP/SSP (SPI, I2C Slave) 20 MHz 8-bit, 5 Channels 1 2K EPROM 128 bytes None -- 28 3 10 MSSP (SPI, I2C Master/Slave) 20 MHz 10-bit, 5 Channels 1 2K FLASH (1,000 E/W cycles) 128 bytes 64 bytes In-Circuit Debugger, Low Voltage Programming PIC16F872 28 3 8 SSP (SPI, I2C Slave) 20 MHz 8-bit, 5 Channels 1 2K FLASH (1000 E/W cycles) 128 bytes None -- PIC16F72
Characteristic Pins Timers Interrupts Communication Frequency A/D CCP Program Memory RAM EEPROM Data Other
2002 Microchip Technology Inc.
DS39597B-page 123
PIC16F72
NOTES:
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DS39597B-page 124
2002 Microchip Technology Inc.
PIC16F72
INDEX A
A/D Acquisition Requirements ........................................... 56 ADCON0 Register....................................................... 53 ADCON1 Register....................................................... 53 ADIF bit ....................................................................... 54 ADRES Register ......................................................... 53 Analog-to-Digital Converter......................................... 53 Associated Registers .................................................. 57 Configuring Analog Port Pins...................................... 56 Configuring the Interrupt ............................................. 54 Configuring the Module............................................... 54 Conversion Clock........................................................ 56 Conversions ................................................................ 56 www..com Converter Characteristics ......................................... 104 Effects of a RESET ..................................................... 57 Internal Sampling Switch (Rss) Impedance ................ 56 Operation During SLEEP ............................................ 57 Source Impedance...................................................... 56 Use of the the CCP Trigger......................................... 57 Absolute Maximum Ratings ................................................ 87 ACK..................................................................................... 49 ADCON0 GO/DONE bit ...................................................... 54 ADRES Register ............................................................. 9, 54 Application Notes AN546 (Using the Analog-to-Digital Converter) .......... 53 AN552 (Implementing Wake-up on Key Strokes Using PIC16F7X) ............................... 23 AN556 (Implementing a Table Read).......................... 19 AN578 (Use of the SSP Module in the I2C Multi-Master Environment)............................... 43 AN607 (Power-up Trouble Shooting) .......................... 64 Assembler MPASM Assembler ..................................................... 81
C
Capture/Compare/PWM ..................................................... 37 Associated Registers with PWM and Timer2.............. 42 Associated Registers, Capture, Compare and Timer1............................................................. 40 Capture CCP1IF............................................................... 38 CCPR1 ............................................................... 38 CCPR1H:CCPR1L.............................................. 38 Capture Mode............................................................. 38 CCP Mode Timer Resources...................................... 37 CCP Pin Configuration ......................................... 38, 39 CCP Prescaler............................................................ 38 CCPR1L Register ....................................................... 37 Compare Mode ........................................................... 39 PWM Mode................................................................. 41 PWM, Example Frequencies/Resolutions .................. 42 Software Interrupt ....................................................... 38 Software Interrupt Mode ............................................. 39 Special Event Trigger and A/D Conversions .............. 39 Special Event Trigger Output of CCP1 ....................... 39 Timer1 Mode Selection......................................... 38, 39 CCPR1H Register............................................................... 37 CCPxM0 bit......................................................................... 37 CCPxM1 bit......................................................................... 37 CCPxM2 bit......................................................................... 37 CCPxM3 bit......................................................................... 37 CCPxX bit ........................................................................... 37 CCPxY bit ........................................................................... 37 CKE .................................................................................... 44 CKP .................................................................................... 45 Clock Polarity Select bit, CKP............................................. 45 Code Examples Changing Between Capture Prescalers ..................... 38 FLASH Program Read................................................ 28 Indirect Addressing..................................................... 19 Initializing PORTA....................................................... 21 Initializing PORTB ...................................................... 23 Initializing PORTC ...................................................... 25 Saving STATUS, W and PCLATH Registers in RAM................................................... 69 Code Protection ............................................................ 59, 72 Configuration Bits ............................................................... 59 Configuration Word............................................................. 60 Conversion Considerations............................................... 123
B
BF ....................................................................................... 44 Block Diagrams A/D .............................................................................. 55 Analog Input Model ..................................................... 55 Capture Mode Operation ............................................ 38 Compare Mode Operation .......................................... 39 In-Circuit Serial Programming Connections................ 72 Interrupt Logic ............................................................. 68 On-Chip Reset Circuit ................................................. 63 PIC16F72...................................................................... 5 PORTC ....................................................................... 25 PWM ........................................................................... 41 RA3:RA0 and RA5 Port Pins ...................................... 21 RA4/T0CKI Pin............................................................ 21 RB3:RB0 Port Pins ..................................................... 23 RB7:RB4 Port Pins ..................................................... 23 Recommended MCLR Circuit ..................................... 63 SSP in I2C Mode......................................................... 48 SSP in SPI Mode ........................................................ 46 Timer0/WDT Prescaler................................................ 29 Timer1 ......................................................................... 32 Timer2 ......................................................................... 35 Watchdog Timer (WDT) .............................................. 70 BOR. See Brown-out Reset Brown-out Reset (BOR) .................................... 59, 62, 65, 66 Buffer Full Status bit, BF ..................................................... 44
D
D/A...................................................................................... 44 Data Memory General Purpose Register File ..................................... 7 Special Function Registers........................................... 9 Data/Address bit, D/A ......................................................... 44 DC and AC Characteristics Graphs and Tables ................................................... 107 DC Characteristics.............................................................. 89 Development Support ......................................................... 81 Device Overview................................................................... 5 Direct Addressing ............................................................... 20
E
Electrical Characteristics .................................................... 87 Errata .................................................................................... 3
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PIC16F72
F
FLASH Program Memory Associated Registers .................................................. 28 Operation During Code Protect................................... 28 Reading....................................................................... 28 FSR Register................................................................... 9, 10 INT Interrupt (RB0/INT). See Interrupt Sources INTCON Register GIE bit......................................................................... 14 INTE bit....................................................................... 14 INTF bit ....................................................................... 14 RBIF bit....................................................................... 14 TMR0IE bit.................................................................. 14 Internal Sampling Switch (Rss) Impedance........................ 56 Interrupt Sources .......................................................... 59, 68 RB0/INT Pin, External................................................. 69 TMR0 Overflow........................................................... 69 Interrupts RB7:RB4 Port Change................................................ 23 Synchronous Serial Port Interrupt............................... 16 Interrupts, Context Saving During....................................... 69 Interrupts, Enable Bits Global Interrupt Enable (GIE bit) .......................... 14, 68 Interrupt-on-Change (RB7:RB4) Enable (RBIE bit) ................................................... 69 RB0/INT Enable (INTE bit) ......................................... 14 TMR0 Overflow Enable (TMR0IE bit) ......................... 14 Interrupts, Flag bits Interrupt-on-Change (RB7:RB4) Flag (RBIF bit) ............................................................... 14 Interrupt-on-Change (RB7:RB4) Flag (RBIF bit) ......................................................... 14, 69 RB0/INT Flag (INTF bit).............................................. 14 TMR0 Overflow Flag (TMR0IF bit).............................. 69
I
I/O Ports .............................................................................. 21 PORTA ........................................................................ 21 PORTB........................................................................ 23 PORTC........................................................................ 25 I2C Associated Registers .................................................. 51 Master Mode ............................................................... 51 Mode Selection ........................................................... 48 www..com Multi-Master Mode ...................................................... 51 SCL and SDA pins ...................................................... 48 Slave Mode ................................................................. 48 ICEPIC In-Circuit Emulator ................................................. 82 ID Locations ........................................................................ 72 In-Circuit Serial Programming (ICSP) ................................. 72 INDF Register ..................................................................... 10 Indirect Addressing ............................................................. 20 FSR Register .............................................................. 19 INDF Register ............................................................. 19 Instruction Format ............................................................... 73 Instruction Set ..................................................................... 73 ADDLW ....................................................................... 75 ADDWF ....................................................................... 75 ANDLW ....................................................................... 75 ANDWF ....................................................................... 75 BCF ............................................................................. 75 BSF ............................................................................. 75 BTFSC ........................................................................ 76 BTFSS ........................................................................ 76 CALL ........................................................................... 76 CLRF........................................................................... 76 CLRW.......................................................................... 76 CLRWDT..................................................................... 76 COMF ......................................................................... 77 DECF .......................................................................... 77 DECFSZ...................................................................... 77 GOTO.......................................................................... 77 INCF............................................................................ 77 INCFSZ ....................................................................... 77 IORLW......................................................................... 78 IORWF ........................................................................ 78 MOVF.......................................................................... 78 MOVLW....................................................................... 78 MOVWF ...................................................................... 78 NOP ............................................................................ 78 RETFIE ....................................................................... 79 RETLW........................................................................ 79 RETURN ..................................................................... 79 RLF ............................................................................. 79 RRF............................................................................. 79 SLEEP ........................................................................ 79 SUBLW........................................................................ 80 SUBWF ....................................................................... 80 Summary Table ........................................................... 74 SWAPF ....................................................................... 80 XORLW ....................................................................... 80 XORWF....................................................................... 80
K
KEELOQ Evaluation and Programming Tools ...................... 84
L
Loading of PC ..................................................................... 18
M
Master Clear (MCLR) MCLR Reset, Normal Operation..................... 62, 65, 66 MCLR Reset, SLEEP...................................... 62, 65, 66 Operation and ESD Protection ................................... 63 Memory Data Memory ................................................................ 7 Program Memory .......................................................... 7 MPLAB C17 and MPLAB C18 C Compilers ....................... 81 MPLAB ICD In-Circuit Debugger ........................................ 83 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ............................ 82 MPLAB Integrated Development Environment Software .................................................. 81 MPLINK Object Linker/MPLIB Object Librarian .................. 82
O
On-Line Support ............................................................... 131 OPCODE Field Descriptions............................................... 73 OPTION_REG Register INTEDG bit ................................................................. 13 PS2:PS0 bits............................................................... 13 PSA bit........................................................................ 13 RBPU bit ..................................................................... 13 T0CS bit...................................................................... 13 T0SE bit ...................................................................... 13
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PIC16F72
Oscillator Configuration................................................. 59, 61 Crystal Oscillator/Ceramic Resonators ....................... 61 HS ......................................................................... 61, 65 LP.......................................................................... 61, 65 RC................................................................... 61, 62, 65 XT ......................................................................... 61, 65 Oscillator, WDT ................................................................... 70 PORTA Register ................................................................... 9 PORTB Associated Registers.................................................. 24 Functions .................................................................... 24 Pull-up Enable (RBPU bit) .......................................... 13 RB0/INT Edge Select (INTEDG bit)............................ 13 RB0/INT Pin, External ................................................ 69 RB7:RB4 Interrupt-on-Change Flag (RBIF bit)........... 14 RB7:RB4 Interrupt-on-Change ................................... 69 RB7:RB4 Interrupt-on-Change Enable (RBIE bit) ............................................................... 69 RB7:RB4 Interrupt-on-Change Flag (RBIF bit) ......................................................... 14, 69 PORTB Register ................................................................... 9 PORTC Associated Registers.................................................. 26 Functions .................................................................... 26 PORTC Register................................................................... 9 Postscaler, WDT Assignment (PSA Bit) ................................................. 13 Rate Select (PS2:PS0 bits) ........................................ 13 Power-down Mode. See SLEEP Power-on Reset (POR)............................... 59, 62, 64, 65, 66 Brown-out Reset (BOR).............................................. 64 Oscillator Start-up Timer (OST) ............................ 59, 64 POR Status (POR bit)................................................. 17 Power Control/Status Register (PCON)...................... 64 Power-down (PD bit) .................................................. 62 Power-up Timer (PWRT) ...................................... 59, 64 Time-out (TO bit) .................................................. 12, 62 Time-out Sequence .................................................... 64 PR2 Register ...................................................................... 35 Prescaler, Timer0 Assignment (PSA bit) ................................................. 13 Rate Select (PS2:PS0 bits) ........................................ 13 PRO MATE II Universal Device Programmer ..................... 83 Product Identification System ........................................... 133 Program Counter RESET Conditions...................................................... 65 Program Memory Paging ........................................................................ 19 Program Memory Map and Stack ......................................... 7 Program Verification ........................................................... 72 PUSH.................................................................................. 19
P
P.......................................................................................... 44 Package Marking Information ........................................... 117 PCFG0 bit ........................................................................... 54 PCFG1 bit ........................................................................... 54 PCFG2 bit ........................................................................... 54 PCL Register............................................................. 9, 10, 18 PCLATH Register ..................................................... 9, 10, 18 www..com PCON Register ................................................................... 64 POR bit ....................................................................... 17 PICDEM 1 Low Cost PICmicro Demonstration Board.................................................... 83 PICDEM 17 Demonstration Board ...................................... 84 PICDEM 2 Low Cost PIC16CXX Demonstration Board.................................................... 83 PICDEM 3 Low Cost PIC16CXXX Demonstration Board.................................................... 84 PICSTART Plus Entry Level Development Programmer ........................................... 83 Pin Functions MCLR/VPP..................................................................... 6 OSC1/CLKI ................................................................... 6 OSC2/CLKO ................................................................. 6 RA0/AN0 ....................................................................... 6 RA1/AN1 ....................................................................... 6 RA2/AN2 ....................................................................... 6 RA3/AN3/VREF .............................................................. 6 RA4/T0CKI.................................................................... 6 RA5/AN4/SS ................................................................. 6 RB0/INT ........................................................................ 6 RB1 ............................................................................... 6 RB2 ............................................................................... 6 RB3 ............................................................................... 6 RB4 ............................................................................... 6 RB5 ............................................................................... 6 RB6/PGC ...................................................................... 6 RB7/PGD ...................................................................... 6 RC0/T1OSO/T1CKI ...................................................... 6 RC1/T1OSI ................................................................... 6 RC2/CCP1 .................................................................... 6 RC3/SCK/SCL .............................................................. 6 RC4/SDI/SDA ............................................................... 6 RC5/SDO ...................................................................... 6 RC6............................................................................... 6 RC7............................................................................... 6 VDD ............................................................................... 6 VSS................................................................................ 6 Pinout Descriptions PIC16F72...................................................................... 6 POP .................................................................................... 19 POR. See Power-on Reset PORTA Associated Registers .................................................. 22 Functions .................................................................... 22
R
R/W..................................................................................... 44 R/W bit ................................................................................ 49 RBIF bit............................................................................... 23 Read/Write bit Information, R/W ......................................... 44 Reader Response............................................................. 132 Reading Program Memory.................................................. 27 PMADR....................................................................... 27 PMCON1 Register...................................................... 27 Receive Overflow Indicator bit, SSPOV.............................. 45 Register File Map.................................................................. 8
2002 Microchip Technology Inc.
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PIC16F72
Registers ............................................................................. 36 ADCON0 (A/D Control 0) ............................................ 53 ADCON1 (A/D Control 1) ............................................ 54 CCPCON1 (Capture/Compare/PWM Control 1) ......... 37 Initialization Conditions (table) .................................... 66 INTCON (Interrupt Control) ......................................... 14 OPTION ...................................................................... 13 PCON (Power Control) ............................................... 17 PIE1 (Peripheral Interrupt Enable 1) ........................... 15 PIR1 (Peripheral Interrupt Flag 1) ............................... 16 PMCON1 (Program Memory Control 1) ...................... 27 SSPCON (Sync Serial Port Control) ........................... 45 SSPSTAT (Synchronous Serial Port Status) ............... 44 STATUS ...................................................................... 12 Summary....................................................................... 9 T1CON (Timer1 Control) ............................................. 31 www..com .......................................................................... 59, 62 RESET Brown-out Reset (BOR). See Brown-out Reset (BOR) MCLR RESET. See MCLR Power-on Reset (POR). See Power-on Reset (POR) RESET Conditions for All Registers............................ 66 RESET Conditions for PCON Register ....................... 65 RESET Conditions for Program Counter .................... 65 RESET Conditions for STATUS Register .................... 65 WDT Reset. See Watchdog Timer (WDT) Revision History ................................................................ 123 RP0, RP1 bit ......................................................................... 7 SSPADD Register............................................................... 10 SSPEN................................................................................ 45 SSPIF ................................................................................. 16 SSPM3:SSPM0 .................................................................. 45 SSPOV ............................................................................... 45 SSPSTAT Register ............................................................. 10 Stack................................................................................... 19 Overflows.................................................................... 19 Underflow ................................................................... 19 START bit, S....................................................................... 44 STATUS Register DC bit.......................................................................... 12 IRP bit ......................................................................... 12 PD bit .......................................................................... 62 TO bit .................................................................... 12, 62 STOP bit, P......................................................................... 44 Synchronous Serial Port (SSP) .......................................... 43 Overview..................................................................... 43 SPI Mode .................................................................... 43 Synchronous Serial Port Enable bit, SSPEN...................... 45 Synchronous Serial Port Interrupt....................................... 16 Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 ............................................................ 45
T
T2CKPS0 bit ....................................................................... 36 T2CKPS1 bit ....................................................................... 36 T2CON (Timer2 Control) .................................................... 36 TAD...................................................................................... 56 Timer0................................................................................. 29 Clock Source Edge Select (T0SE bit)......................... 13 Clock Source Select (T0CS bit) .................................. 13 External Clock............................................................. 30 Interrupt ...................................................................... 29 Operation .................................................................... 29 Overflow Enable (TMR0IE bit) .................................... 14 Overflow Flag (TMR0IF bit) ........................................ 69 Overflow Interrupt ....................................................... 69 Prescaler .................................................................... 30 T0CKI ......................................................................... 30 Timer1 Associated Registers .................................................. 34 Asynchronous Counter Mode ..................................... 33 Capacitor Selection..................................................... 33 Counter Operation ...................................................... 32 Interrupt ...................................................................... 33 Operation in Timer Mode ............................................ 32 Oscillator..................................................................... 33 Prescaler .................................................................... 34 Resetting TMR1H, TMR1L Register Pair.................... 34 Resetting Using a CCP Trigger Output....................... 33 Synchronized Counter Mode ...................................... 32 Timer2................................................................................. 35 Interrupt ...................................................................... 35 Operation .................................................................... 35 Output ......................................................................... 35 Prescaler, Postscaler .................................................. 35
S
S.......................................................................................... 44 Sales and Support............................................................. 133 Slave Mode SCL ............................................................................. 48 SDA............................................................................. 48 SLEEP..................................................................... 59, 62, 71 SMP .................................................................................... 44 Software Simulator (MPLAB SIM)....................................... 82 Special Event Trigger.......................................................... 57 Special Features of the CPU............................................... 59 Special Function Registers PMADRH .................................................................... 27 PMADRL ..................................................................... 27 PMCON1..................................................................... 27 PMDATH ..................................................................... 27 PMDATL...................................................................... 27 SPI Associated Registers .................................................. 46 SPI Clock Edge Select bit, CKE.......................................... 44 SPI Data Input Sample Phase Select bit, SMP................... 44 SPI Mode Serial Clock ................................................................. 43 Serial Data In .............................................................. 43 Serial Data Out............................................................ 43 Slave Select ................................................................ 43 SSP ACK............................................................................. 48 Addressing .................................................................. 48 BF bit........................................................................... 48 I2C Mode Operation .................................................... 48 R/W bit ........................................................................ 49 Reception .................................................................... 49 SCL Clock Input .......................................................... 48 SSPOV bit ................................................................... 48 Transmission............................................................... 49
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PIC16F72
Timing Diagrams A/D Conversion......................................................... 105 Brown-out Reset ......................................................... 96 Capture/Compare/PWM (CCP1)................................. 98 CLKO and I/O ............................................................. 95 External Clock............................................................. 94 I2C Bus Data ............................................................. 102 I2C Bus START/STOP bits........................................ 101 I2C Reception (7-bit Address) ..................................... 50 I2C Transmission (7-bit Address) ................................ 50 RESET, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer............................................... 96 Slow Rise Time (MCLR Tied to VDD Through RC Network)........................................................... 68 SPI Master Mode ........................................................ 47 SPI Master Mode (CKE = 0, SMP = 0) ....................... 99 www..com SPI Master Mode (CKE = 1, SMP = 1) ....................... 99 SPI Slave Mode (CKE = 0) ................................. 47, 100 SPI Slave Mode (CKE = 1) ................................. 47, 100 Time-out Sequence on Power-up (MCLR Tied to VDD Through Pull-up Resistor)............................... 67 Time-out Sequence on Power-up (MCLR Tied to VDD Through RC Network): Case 1 ....................... 67 Time-out Sequence on Power-up (MCLR Tied to VDD Through RC Network): Case 2 ....................... 67 Timer0 and Timer1 External Clock.............................. 97 Wake-up from SLEEP through Interrupt ..................... 72 Timing Parameter Symbology............................................. 93 TMR1H Register ................................................................... 9 TMR1L Register .................................................................... 9 TMR2 Register ...................................................................... 9 TMR2ON bit ........................................................................ 36 TOUTPS0 bit....................................................................... 36 TOUTPS1 bit....................................................................... 36 TOUTPS2 bit....................................................................... 36 TOUTPS3 bit....................................................................... 36 TRISA Register ............................................................. 10, 21 TRISB Register ............................................................. 10, 23 TRISC Register ............................................................. 10, 25
U
UA....................................................................................... 44 Update Address bit, UA ...................................................... 44
W
Wake-up from SLEEP................................................... 59, 71 Interrupts .............................................................. 65, 66 MCLR Reset ............................................................... 66 WDT Reset ................................................................. 66 Watchdog Timer (WDT)................................................ 59, 70 Associated Registers.................................................. 70 Enable (WDTEN bit) ................................................... 70 Postscaler. See Postscaler, WDT Programming Considerations ..................................... 70 RC Oscillator .............................................................. 70 Time-out Period .......................................................... 70 WDT Reset, Normal Operation....................... 62, 65, 66 WDT Reset, SLEEP ....................................... 62, 65, 66 WCOL ................................................................................. 45 Write Collision Detect bit, WCOL........................................ 45 WWW, On-Line Support ....................................................... 3
2002 Microchip Technology Inc.
DS39597B-page 129
PIC16F72
NOTES:
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DS39597B-page 130
2002 Microchip Technology Inc.
PIC16F72
ON-LINE SUPPORT
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The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world.
013001
Connecting to the Microchip Internet Web Site
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The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
2002 Microchip Technology Inc.
DS39597B-page 131
PIC16F72
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
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Application (optional): Would you like a reply? Device: PIC16F72 Questions: 1. What are the best features of this document? Y N Literature Number: DS39597B
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
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DS39597B-page 132
2002 Microchip Technology Inc.
PIC16F72
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b)
Device PIC16F72: Standard VDD range PIC16F72T: (Tape and Reel) PIC16LF72: Extended VDD range PIC16F72-04I/SO = Industrial Temp., SOIC package, normal VDD limits PIC16LF72-20I/SS = Industrial Temp., SSOP package, extended VDD limits PIC16F72-20I/ML = Industrial Temp., QFN package, normal VDD limits
c)
Temperature Range
I
= =
0C to +70C -40C to +85C
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Package SO SS ML P = = = = SOIC SSOP QFN PDIP
Pattern
QTP, SQTP, ROM Code (factory specified) or Special Requirements. Blank for OTP and Windowed devices.
*
JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
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DS39597B-page 133
M
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05/16/02
DS39597B-page 134
2002 Microchip Technology Inc.

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